The CCS C Compiler now support the PIC18F24K42 family of devices. Currently available devices have up to 32 KB of Program Flash Memory, 256 B of Data EEPROM and up to 2 KB of Data SRAM. Additionally they have 25 I/O pins, 24 12-bit ADC channels, 1 5-bit DAC, 2 Comparators, 3 8-bit Timers, 3 16-bit Timers, Windowed Watchdog Timer, Signal Measurement Timer (SMT), 4 CCP peripherals, 4 10-bit PWM peripherals, 3 Complementary Waveform Generators (CWG), Numerically Controlled Oscillator (NCO), 4 CLC peripherals, Zero-Cross Detect, 2 UART peripherals, 2 I2C peripherals and 1 SPI peripheral.
Additionally each of the I/O pins can be assigned to almost any peripheral using the CCS C Compiler's #pin_select directive make it highly configurable for your specific hardware implementation. Future devices in this family will have up to 128 KB of Program Flash Memory, up to 1 KB of Data EEPROM, up to 8 KB for Data SRAM, up to 44 I/O pins and up to 43 ADC channels. 8KB of RAM is a significant upgrade for the PIC18 family, as previously the architecture only supported 4KB of RAM.
The newest feature that this family has is an optionally enabled interrupt vector table (IVT). The IVT allows for quicker entry into a peripheral's interrupt service routine (ISR). Normally the compiler has to search through the interrupt enable and interrupt flag bits to determine which peripheral caused the interrupt in order jump to the correct ISR. When the IVT is enabled each interrupt has a specific address it will go to when an interrupt occurs which contains the address of that peripheral's ISR, which makes servicing the ISR faster. The IVT can be enabled for these device in the CCS C Compiler by adding #device vector_ints to the code for this family of devices.
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