Enhanced 8-bit Mid-Range Core

Enhanced Midrange Core

  • Support Now available in PCM Compilers
  • Reduce Production costs by at least 15% per chip
  • Gain 16 levels hardware stack
  • Increased Instruction Count
  • More Program Memory
  • Increased Peripheral Support
Gain Access to NEW Compiler Features
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Customers on Active Maintenance are eligible for support at NO ADDITIONAL COST! Please visit the compiler downloads page.

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Customers new to CCS can obtain support by purchasing a PCM, PCW, PCWH or PCWHD Compiler.

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Complete Architecture Support
New PIC®MCU Architecture Features New CCS Compiler Support

Up to 56K of Flash Program Memory and 4k Data Memory

Enhanced 16-level hardware stack with optional RESET

Increased peripheral support including:

  • Multiple A/D converters & comparators
  • Multiple SPI/I2C, USART
  • Multiple capture/compare/PWM
  • *mTouch™ & Non-Volatile Memory
  • Operational amplifiers & LCD drive capability

Enhanced Indirect linear addressing

C programming language optimizations

Automatic interrupt context save of core registers

Simplified register map

Additional Features Include:

  • Up to 32MHz internal oscillator
  • Low power 1.8V operation up to 5.5V

Support for parts with up to 56K instructions and 4K of RAM

Reduction of inlined system functions with the 16-level call stack

New Built-in Functions for ALL enhanced peripherals:

Uses MOVLP for page switches and MOVLB for bank switches

  • Inline assembler supports all new instructions and addressing modes
  • Full implementation of ANSI setjmp.h functions utilizing the new stack access
  • Uses SFRs to reduce the number of instructions needed for complex expression

Reduced interrupt overhead

Compatibility switch to translate old or hard-coded addresses, to new SFR registers

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Compiler Exploitation of the New Instructions


New from Microchip

Enhanced Mid-Range Core Architecture Support Info