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How to run dspic33ep256mu806 at maximum MIPS?
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Ttelmah



Joined: 11 Mar 2010
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PostPosted: Mon Jan 12, 2015 3:00 am     Reply with quote

Oxo, I don't see any diode on the Vdd line. This means the programmer (assuming it is supplying power), will be trying to power any other circuitry on the line. Could be a problem. Obviously your 'debug enable' jumper is really 'debug disable'. Must be open for debug operation. Depending on the PCB layout on the MCLR, PGC, and PGD lines, you might be suffering from overshoot on these. Series 100R resistors are often recommended. R46, is lower than really necessary or desirable, and might encourage a problem.

Basically looks right.
oxo



Joined: 13 Nov 2012
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PostPosted: Mon Jan 12, 2015 3:55 am     Reply with quote

That's ok TT, I run the ICD-U64 from the target hardware supply.

I have popped R45 off the board, so the MCLR is solely run from the ICD.

Still no luck.

The CCSLOAD diagnostics check out the PGC,PGD and MCLR lines and they are connected ok. Getting a bit stuck now.

Is anyone using this chip with the latest software, CCSLOAD 5.07 ?
Ttelmah



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PostPosted: Mon Jan 12, 2015 6:07 am     Reply with quote

Yes. Sensible things to try. What is the actual board supply voltage?. You show 3.3v, but have you measured it at the chip?. What sort of larger reservoir capacitors are there on this supply?.
oxo



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PostPosted: Tue Jan 13, 2015 2:05 am     Reply with quote

TT,

Supply measured is 3.28

There is ~20 uF on the 3.3 rail comprising 2 x 4.7u and 1 x 10u, plus a whole load of decouplers..

This board is based on previous design, and the main difference is changing from Pic18 to this dsPIC33.
Ttelmah



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PostPosted: Wed Jan 14, 2015 2:04 am     Reply with quote

Good.
I was querying, since I've seen a couple of the DsPIC's that won't actually erase if the supply is down at about 3.1v. They are much more fussy, than the data sheet implies....
oxo



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PostPosted: Wed Jan 14, 2015 2:10 am     Reply with quote

Interesting..

But I am still stalled on fixing this.

I have contacted CCS with no reply as yet.

They have a dev kit with this cpu ( http://www.ccsinfo.com/product_info.php?products_id=dsPIC-analog-kit ), and i have asked them to confirm it all works with the latest ccsload.

I also asked them to show me their schematic in case they use different debug pins. I am using PGEC1/PGED1 and I have tried PGEC3/PGED3, all with no success.

My current best guess is that its a ccsload or a problem with my ICD-U64, although they both work with the explorer16 and a different variant of dsPIC33.
Ttelmah



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PostPosted: Wed Jan 14, 2015 3:49 am     Reply with quote

Sounds a sensible way to proceed. Hope they get back to you quickly. Given it's a 'supplied' unit, with the development tool they ship, it really should work!.
I see they even supply the 'wall wart'. I was going to suggest trying another supply - just had two D-link that were 'spiking' when loaded a little....
What happens if you tell the programmer to supply power?. Remember some people finding the units behaved differently when you did.
oxo



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PostPosted: Tue Feb 03, 2015 9:22 am     Reply with quote

So, to close off my part of this topic.. we found what was wrong.

This CPU has a limit of 300mv maximum difference between VDD and AVVD during power up. We were running dual regulators with separate supplies, and they were not coming up within that limit. Connect both to the same supply, and it all works fine.
Ttelmah



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PostPosted: Tue Feb 03, 2015 9:56 am     Reply with quote

At least you now have it going.

Separate rails, has been mentioned before as giving problems on a thread some time ago. I think somebody suggested putting Schottky diodes so that the 'slow' rail was guaranteed to not get too far behind the faster one.
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