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homfray
Joined: 19 Nov 2003
Posts: 45
Location: Oxford
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| enable / disable I2C interrupt ( 18F452 ) |
 Posted: Thu May 20, 2004 4:08 am |
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I am using the I2C slave code as it is in
http://www.ccsinfo.com/forum/viewtopic.php?t=14473&
and it works fine. I would like to disable the i2c interrupt and do other activities but using the following code it either enables the interrupt whatever the input state or disables the interrupt whatever the input state.
What code changes are needed to either disable or enable the i2c interrupt on this slave code
| Code: | void main()
{
int i;
for(i=1;i< BUF_LEN;i++)
buf[i] = i;
setup_wdt(WDT_OFF);
set_tris_b(0); // Set port b for output for debugging
init_i2c(); // Set i2c slave mode, slave address, enable SSP
enable_interrupts(int_ssp);
enable_interrupts(global);
// Loop continuously
while(1)
{
delay_ms(100);
if (input(ONOFF))
enable_interrupts(int_ssp);
else
disable_interrupts(int_ssp);
}
}
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lucky
Joined: 12 Sep 2003
Posts: 46
Location: South Coast - England
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| I2C int |
| Posted: Thu May 20, 2004 6:30 am |
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Thats correct then add you slave I2C code into a function like:
#int_ssp
I2C_Interrupt(){
// Put code here
}
This function will get called when there is I2C activity.
_________________
Lucky
www.mpic3.com - MPIC3 player project, Forum, Downloads, Online Shop |
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Guest
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| Posted: Thu May 20, 2004 7:27 am |
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I didn't think to include all the code (interrupt now included at bottom) as I already have the interrupt working. when I just enable it and leave it, it works fine. What I can't do is to enable or disable the intterrupt by using
| Code: | if (input(ONOFF))
enable_interrupts(int_ssp);
else
disable_interrupts(int_ssp); |
what do I need to do??
| Code: | #int_SSP
SSP_isr()
{
// Keep only bits D/A, S, R/W, BF
switch (SSPSTAT & 0x2d)
{
case(STATE1):
output_bit(PIN_B5, state);
state=~state;
// Master write operation, address byte in SSPBUF.
// Clear the data buffer. Keep Master waiting by clock stretching for this
// to finish before it sends data byte(s). Otherwise SSPBUF will be full
// and an acknowledge will not be generated by the slave i2c hardware.
CKP = 0; // Make Master wait by holding SCL low
//for (buf_index = 0; buf_index < BUF_LEN; buf_index++) {
//buf[buf_index] = 0;
//}
buf_index = 0; // Reset the data buffer index
SSPOV = 0; // Clear receive overflow flag, could be set from last
// time because after not /ack, SSPBUF was still full.
buf[buf_index] = SSPBUF; // Dummy read to clear BF (read only bit)
CKP = 1; // Allow master to continue by re-enabling SCL
break;
case(STATE2):
output_bit(PIN_B5, state);
state=~state;
buf_index++;
// Master write operation, data byte in SSPBUF
// If previous byte in SSPBUF not read, NACK sent back to master
// Get data byte, also clears BF
SSPOV = 0; // Same comment as for State1
buf[buf_index] = SSPBUF;
CKP = 0; // Make Master wait by holding SCL low
//delay_ms(100); // As necessary for the particular application
output_b(buf[buf_index]); // For debugging
// Wrap around, should never occur
if (buf_index > BUF_LEN) buf_index = 0;
CKP = 1; // Allow master to continue by re-enabling SCL
break;
case(STATE3):
output_bit(PIN_B5, state);
state=~state;
// Master has begun new read operation by initiating a START or RESTART
// then sending Slave address (read) byte (now in SSPBUF).
// Looks like clock enable bit CKP cleared on interrupt, so must
// set it again to allow Master to clock data byte out.
CKP = 0; // Make Master wait by holding SCL low
// Master can be kept waiting here if necessary.
// delay_ms(5000); // For testing clock stretching only
buf_index = 0; // Reset buffer index
SSPBUF = buf[buf_index]; // Load 1st byte from data buffer
buf_index++;
CKP = 1; // Enable SCL for Master to shift byte out
break;
case(STATE4):
output_bit(PIN_B5, state);
state=~state;
// Master read operation, last byte was data, SSPBUF empty.
// Move next byte to SSPBUF and SSPSR.
// Same comment for CKP bit as in STATE3.
CKP = 0; // Make Master wait by holding SCL low
SSPBUF = buf[buf_index]; // Get next byte from data buffer
buf_index++;
if (buf_index > BUF_LEN) buf_index = 0;
CKP = 1; // Enable SCL for Master to shift byte out
break;
case(STATE5):
output_bit(PIN_B5, state);
state=~state;
// A not /ack (high) was received from Master in response to data
// byte received from Slave (last byte). Slave i2c logic is reset,
// and waits for next Master operation.
break;
default:
output_bit(PIN_B5, state);
state=~state;
// Error, trap here. Watchdog will reset pic (must be enabled, and
// watchdog timer cleared in other loops).
while(1);
break;
}
} |
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lucky
Joined: 12 Sep 2003
Posts: 46
Location: South Coast - England
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| I2C Slave Address |
| Posted: Fri May 21, 2004 1:41 am |
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Oh, Thats a strange one.
Have you looked at the listing file?
_________________
Lucky
www.mpic3.com - MPIC3 player project, Forum, Downloads, Online Shop |
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