CCS C Software and Maintenance Offers
FAQFAQ   FAQForum Help   FAQOfficial CCS Support   SearchSearch  RegisterRegister 

ProfileProfile   Log in to check your private messagesLog in to check your private messages   Log inLog in 

CCS does not monitor this forum on a regular basis.

Please do not post bug reports on this forum. Send them to CCS Technical Support

I2C master and slave without interrupts …

 
Post new topic   Reply to topic    CCS Forum Index -> General CCS C Discussion
View previous topic :: View next topic  
Author Message
asmallri



Joined: 12 Aug 2004
Posts: 1642
Location: Perth, Australia

View user's profile Send private message Send e-mail Visit poster's website

I2C master and slave without interrupts …
PostPosted: Wed Apr 23, 2025 9:22 am     Reply with quote

I have a requirement to connect two PIC24FJ128GA010 PICs together via an I2C bus with either PIC using interrupts. While they are communicating via I2C neither PIC is performing any other tasks.

I did this successfully and reliably 10 years ago using the Microchip C30 compiler but after many days I have not been able to replicate this using the PCD compiler. I believe the issue is on the slave side. I thought I could use the CCS i2c_isr_state() by enabling the I2C module, setting up the I2C bus using the #use i2c directive, enabling the I2C module setting the I2CEN bit, enabling I2C receive via the RCEN bit, polling the IFRx registers SI2CIF flag and then calling the i2c_isr_state() whenever the flag is set, and then perform the standard state processing that would typically be done in the interrupt handler.

If i perform an i2Cscanner function it correctly sees the slave PIC but any attempt to perform read or writes to the slave fail with the slave address with the master seeing a NACK condition as soon as the puts the Slave address on the bus. I have a logic analyser on the bus and the I2C bus itself seems fine.

Has anyone tried running masters and slaves together like this wiithout using interrupts?
_________________
Regards, Andrew

http://www.brushelectronics.com/software
Home of Ethernet, SD card and Encrypted Serial Bootloaders for PICs!!
allenhuffman



Joined: 17 Jun 2019
Posts: 620
Location: Des Moines, Iowa, USA

View user's profile Send private message Visit poster's website

PostPosted: Wed Apr 23, 2025 9:58 am     Reply with quote

I have done non-IRQ implementations of Slave I2C code on PIC24, and we have one board that uses IRQs for its slave, then is non-IRQ Master mode to talk to a secondary I2C bus.

I used CCS' i2c_state() but then used a few bits in the registers to know when the STOP bit was seen so the slave knew when it was time to stop reading incoming data.
_________________
Allen C. Huffman, Sub-Etha Software (est. 1990) http://www.subethasoftware.com
Embedded C, Arduino, MSP430, ESP8266/32, BASIC Stamp and PIC24 programmer.
http://www.whywouldyouwanttodothat.com ?

Using: 24FJ256GA106, 24EP256GP202 and 24FJ64GA002.
asmallri



Joined: 12 Aug 2004
Posts: 1642
Location: Perth, Australia

View user's profile Send private message Send e-mail Visit poster's website

PostPosted: Wed Apr 23, 2025 11:06 am     Reply with quote

Thanks Allen, I will keep digging..
_________________
Regards, Andrew

http://www.brushelectronics.com/software
Home of Ethernet, SD card and Encrypted Serial Bootloaders for PICs!!
Ttelmah



Joined: 11 Mar 2010
Posts: 19803

View user's profile Send private message

PostPosted: Thu Apr 24, 2025 12:13 am     Reply with quote

There is fundamentally nothing 'different' about doing a slave without
interrupts. Just poll the interrupt flag, and clear it when you handle it
'interrupt_active', and 'clear_interrupt'. The key thing and problem
is that you need to be polling the flag at quite short intervals if it
isn't going to lead to a problem (actually I2C is not bad in this regard,
since the slave will hold the clock till a byte is read - SMBUS is harder here
since it has a timeout). The master normally does not use interrupts at all,
but the slave can lead to issues from the master if the delays become
long.
You also need to be excruciatingly careful to ensure the I2C is setup to
clock stretch, and you handle not releasing this for things like a master
read from the slave, till the byte is loaded (this is the default use in the
standard ISR handler).
Just generate the standard ISR routine, and have a 'TEST_I2C' macro, that
tests if the interrupt is active, and calls the routine if it is. Add to the handler
a clear_interrupt at the end. Place this macro at regular intervals in your
code.
Display posts from previous:   
Post new topic   Reply to topic    CCS Forum Index -> General CCS C Discussion All times are GMT - 6 Hours
Page 1 of 1

 
Jump to:  
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum


Powered by phpBB © 2001, 2005 phpBB Group