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12F1840 Baudrate not setup with BRG16=1 ?

 
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nurquhar



Joined: 05 Aug 2006
Posts: 149
Location: Redditch, UK

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12F1840 Baudrate not setup with BRG16=1 ?
PostPosted: Mon Jan 06, 2020 4:31 am     Reply with quote

CCS version 5.025

I have been working on an application which uses the USART on the 12F1840 at 115,200 baud.

I used these values to setup the USART:
Code:

#use delay(INTERNAL=32MHz)

// Default Uart TX = A0, RX = A1
// Alternate Uart TX = A4, RX = A5
#use rs232(UART1, baud=115200,parity=N,bits=8,stop=1, ERRORS)

When I print out the relevant registers for the baud rate I see CCS has done it with these values :

    SYNC=0, BRGH=1, BRG16=0, SPBRG=16

According to the 12F1840 datasheet (p281) it is working with an error rate of 2.12% and an actual rate of of 117.64k

HOWEVER
The datasheet says on page 283 that with BRGH=1 and BRG16=1 and an SPBRG value of 68 you can get an error rate of just 0.68% !!

So why does the compiler not use this better option for the 12F1840 ?

As additional information I got here by wanting to reduce the clock rate to 8Mhz instead of 32MHz but CCS refused to compile even though as stated on page 283 that 115,200 can be achieved with an error 2.12% if you use BRGH=1 and BRG16=1.

If I change the device to the similar part 16F1825 then you can get CCS to compile for 115,200 baud @ 8Mhz. So does CCS not know the 12F1840 has the BRG16 bit ?

If I force my own setting of BRGH=1, BRG16=1 and SPBRG=68 then the USART works fine at 115,200, as it also does with the CCS setup but mine is more accurate I assume. Also I can reduce my clock to 8Mhz if I force my own baud rate 115,200 USART setup. Where as CCS says it can't be done.

I am using an old version of CCS Compiler 5.025 so perhaps this has been fixed since.
PCM programmer



Joined: 06 Sep 2003
Posts: 21708

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PostPosted: Mon Jan 06, 2020 4:41 am     Reply with quote

Here is the UART init code for vs. 5.091:
Code:
.... void main(void)
000A:  MOVLW  F0
000B:  MOVLB  01
000C:  MOVWF  OSCCON
000D:  MOVLB  00
000E:  CLRF   rs232_errors
000F:  MOVLB  03

0010:  BSF    BAUDCON.BRG16  // Set BRG16 = 1
0011:  MOVLW  44               // 68 decimal
0012:  MOVWF  SP1BRGL
0013:  MOVLW  00
0014:  MOVWF  SP1BRGH
0015:  MOVLW  A6
0016:  MOVWF  TXSTA     // Set BRGH = 1 
0017:  MOVLW  90
0018:  MOVWF  RCSTA

0019:  CLRF   ANSELA
001A:  MOVLB  02
001B:  CLRF   CM1CON1
001C:  CLRF   CM1CON0
nurquhar



Joined: 05 Aug 2006
Posts: 149
Location: Redditch, UK

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PostPosted: Mon Jan 06, 2020 4:47 am     Reply with quote

Yes thanks for the quick test to confirm the CCS bug is now fixed. Looks like I should throw some money in the direction of CCS.
Ttelmah



Joined: 11 Mar 2010
Posts: 19195

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PostPosted: Mon Jan 06, 2020 6:22 am     Reply with quote

It was fixed quite a long time ago. It was just that the algorithm they used
was written originally for chips that didn't offer BRG16 as an option.
When these started to become common, they changed this, but for
quite a while this option was not used.
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