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Measuring VBG (bandgap voltage ref) on PIC24FJ12GB204

 
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JamesW



Joined: 23 Apr 2007
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Measuring VBG (bandgap voltage ref) on PIC24FJ12GB204
PostPosted: Fri Feb 02, 2018 10:15 am     Reply with quote

Hi folks,

Has anyone had any success measuring the 1.2V bandgap reference using the ADC on a PIC24FJ12GB204?

I don't think I am doing anything that wrong, but I'm getting some very weird results. (CCS support are also looking into this).

Processor setup

Code:

#include <24FJ128GB204.h>
#device PASS_STRINGS = IN_RAM
#case
#device ADC=12
#device ICSP=1
#use delay(internal=32MHz, USB_FULL,restart_wdt)
#BIT VBGEN=getenv("BIT:VBGEN")



ADC Setup
Code:

setup_adc_ports(sAN10, VSS_VDD);

setup_adc(ADC_CLOCK_INTERNAL | ADC_TAD_MUL_0);


Bit where I actually read it
Code:

   /* ENABLE THE BAND GAP VOLTAGE REFERENCE */
   VBGEN = TRUE;
   
   set_adc_channel(28);
   delay_us(20);
   BandGapADC = read_adc();
   fprintf(DEBUG_PORT, "\r\nBAND GAP:%04u", BandGapADC);

.

The voltage level on my processor is 3.3437V.

By that rationale if I am reading the band gap voltage (which according to the datasheet is 1.2V) I should expect to see 35.8% of the full scale value of the A/D converter (running in 12 bit mode) when I read from channel 28. So I should expect to see a reading of 1466.

However :
With the ADC_TAD_MUL_0 set – I get a reading of 2917
With the ADC_TAD_MUL_31 set – I get a reading of 1939 instead.

Neither of these is even close to the 1466 I am expecting.


Unless of course I am being an idiot, and I'm always willing to eat humble pie if it solves the problem!


Thanks in advance

James
Ttelmah



Joined: 11 Mar 2010
Posts: 12633

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PostPosted: Fri Feb 02, 2018 1:20 pm     Reply with quote

I'd set the BGREQ bit as well. Otherwise the band gap may not actually be on.

As a comment, you need ACT=USB added to your clock setup if you intend to use the USB.
PCM programmer



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Posts: 20136

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PostPosted: Fri Feb 02, 2018 2:42 pm     Reply with quote

Put a delay after you enable the band gap generator. See what happens.
Quote:

VBGEN = TRUE;

delay_ms(10); // *** Add this line

set_adc_channel(28);
delay_us(20);
BandGapADC = read_adc();
fprintf(DEBUG_PORT, "\r\nBAND GAP:%04u", BandGapADC);
JamesW



Joined: 23 Apr 2007
Posts: 60
Location: Rochester, England

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PostPosted: Mon Feb 05, 2018 7:58 am     Reply with quote

Hi Folks,

Thanks for the help as always.

I have stuck the above code changes in, and it makes absolutely no difference.

My ADC reading is 2913

However I then had an email from Richard @ ccs support, who has found this. . .


To get the correct VBG reading I had to increase the sampling time. To do that I had to use a slower ADC clock, surprisingly the internal clock was to fast, a 1ms ADC clock period with a sampling time of 31 Tad seem to work for me. For example with a clock speed of 32MHz the following ADC setup worked for me to read it correctly:


Code:

setup_adc(ADC_CLOCK_DIV_32 | ADC_TAD_MUL_31);


originally I had this setup

Code:

 setup_adc(ADC_CLOCK_INTERNAL | ADC_TAD_MUL_31);


Under the new settings I get an ADC value of this....

BAND GAP:1479


Which is pretty much where I'd expect it to be.


However - I am at a loss to explain why! Any ideas?

Thanks

James
temtronic



Joined: 01 Jul 2010
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PostPosted: Mon Feb 05, 2018 8:03 am     Reply with quote

this
setup_adc(ADC_CLOCK_INTERNAL

most PICs 'internal' is ONLY supposed to be used for sleeping PICs..it's somewhere in the ADC section, a chart or table, that shows valid adc clock vs CPU clock...usually there's 2 or 3 valid settings you can use.

the div_31 is interesting to me... 32 makes sense, 31 is just 'odd' though I don't use that PIC so I'll assume it's a correct value

Jay
Ttelmah



Joined: 11 Mar 2010
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PostPosted: Mon Feb 05, 2018 9:43 am     Reply with quote

temtronic wrote:
this
setup_adc(ADC_CLOCK_INTERNAL

most PICs 'internal' is ONLY supposed to be used for sleeping PICs..it's somewhere in the ADC section, a chart or table, that shows valid adc clock vs CPU clock...usually there's 2 or 3 valid settings you can use.

the div_31 is interesting to me... 32 makes sense, 31 is just 'odd' though I don't use that PIC so I'll assume it's a correct value

Jay


I'm sorry Jay, this is wrong for the PIC24's.
The internal clock is often recommended.

I originally was going to suggest increasing the divider, since some other chips in the family have the internal RC too fast without a divider, and /2 has to be selected. However I checked the data sheet, and for this chip it is specific that the internal clock is slow enough.
Looks like a case where the data sheet is wrong for this chip.... Sad

On several of the other chips there is advice _not_ to have a TAD_MUL of 0. However '1' is enough if you have the delay as you do.

I'd suggest:

setup_adc(ADC_CLOCK_DIV_2 | ADC_TAD_MUL_1);

Might well work (assuming you have the acquisition delay you show in your code).
PCM programmer



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PostPosted: Mon Feb 05, 2018 11:15 am     Reply with quote

There is a related errata on this PIC, though it's for reading VBG/2:
Quote:
2. Module: A/D Converter
Incorrect VBG/2 voltage measurement of the A/D
Converter at full speed.

When the A/D Converter is converting at full speed
(500 ksps for 10-bit and 200 ksps for 12-bit), the
A/D Converter count may not match the VBG/2 voltage.

Work around:
The A/D Converter clock should be lowered to
below 100 ksps (in 12-bit mode) to read the correct
value of the VBG/2 voltage. In 10-bit mode,
the clock must be lowered to below 200 ksps.

http://ww1.microchip.com/downloads/en/DeviceDoc/80000613e.pdf
Ttelmah



Joined: 11 Mar 2010
Posts: 12633

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PostPosted: Mon Feb 05, 2018 11:43 am     Reply with quote

Yes. I had seen that one.
It definitely looks like one that MicroChip should be told about.
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