Re: SPI as slave

[jim]

I have my PIC16F877 set up as a slave.
setup_spi(SPI_SLAVE | SPI_L_TO_H | SPI_CLK_DIV_16);


i have my I/O ports set up corectly for a slave.
set_tris_a(0x20);
set_tris_c(0x08);

this is what i am doing to read the spi
if(spi_data_is_in())
data = spi_read();


I have a free running external clock from another device, which is connected to my CLK pin. the data out from the device is connected to my SDI pin. now there is a sync pulse from the external device when it is ready to send the data.

according to the data book the SS line could be used to allow the external clock to route to the SSPSR reg. when high and stop the clock when low.

that is the way I read it anyway. Page 65

no matter what logic level I put on the SS pin it does not stop the SSPSR reg. from being clocked. the SSPSR register always receives the clock and therefore my data never gets synced up.

anyone have any ideas on how I can do this, I need to stop the SSPSR register from being clocked so my data always start msb. not some indeterminate bit in the register.
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This message was ported from CCS's old forum
Original Post ID: 90

[PCM programmer]

:=I have my PIC16F877 set up as a slave.
:=setup_spi(SPI_SLAVE | SPI_L_TO_H | SPI_CLK_DIV_16);
---------------------------------------------------

You shouldn't use the clock divider value in slave mode.
The compiler is OR'ing in those bits, and it's screwing
up the SPI mode. It's disabling the /SS function.

Try it like this:
setup_spi(SPI_SLAVE | SPI_L_TO_H);

That should at least let /SS work.
(I didn't look at it any further than this).
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This message was ported from CCS's old forum
Original Post ID: 91

[Marcelo]

Yea, the block diagram does show that a 0 on the AND would stop the clock but with as little as I understand about what you're trying to do, it doesn't seem that it should matter if it continues to clock because you're not getting meaninful data until the sync pulse anyway. You shouldn't be putting anything into the SS line. If you're in slave mode then it's an input and it's what syncs your incoming byte. If your sync pulse looks anything like the sample ones on page 69 then you should not have a problem.

:=I have my PIC16F877 set up as a slave.
:=setup_spi(SPI_SLAVE | SPI_L_TO_H | SPI_CLK_DIV_16);
:=
:=
:=i have my I/O ports set up corectly for a slave.
:= set_tris_a(0x20);
:= set_tris_c(0x08);
:=
:=this is what i am doing to read the spi
:=if(spi_data_is_in())
:= data = spi_read();
:=
:=
:=I have a free running external clock from another device, which is connected to my CLK pin. the data out from the device is connected to my SDI pin. now there is a sync pulse from the external device when it is ready to send the data.
:=
:=according to the data book the SS line could be used to allow the external clock to route to the SSPSR reg. when high and stop the clock when low.
:=
:=that is the way I read it anyway. Page 65
:=
:=no matter what logic level I put on the SS pin it does not stop the SSPSR reg. from being clocked. the SSPSR register always receives the clock and therefore my data never gets synced up.
:=
:=anyone have any ideas on how I can do this, I need to stop the SSPSR register from being clocked so my data always start msb. not some indeterminate bit in the register.
___________________________
This message was ported from CCS's old forum
Original Post ID: 261