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dsPIC33fj128MC804 header

 
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wangine



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dsPIC33fj128MC804 header
PostPosted: Wed Aug 31, 2011 2:13 pm     Reply with quote

Header dsPIC33fj128MC804 full functional access to the registry and supports independent and functions of C30 did CCS compiler.
I hope to be helpful.
success
[code:1:a35a3eccc5]
//////// Standard Header file for the DSPIC33FJ128MC804 device ////////////////
#device DSPIC33FJ128MC804
#nolist
//////// Program memory: 44032x24 Data RAM: 16384 Stack: 31
//////// I/O: 35 Analog Pins: 9
//////// Fuses: WRTB,NOWRTB,BSSH1792,BSSH768,BSSH256,BSSS1792,BSSS768
//////// Fuses: BSSS256,NOBSS,RBS1024,RBS256,RBS128,NORBS,WRTSS,NOWRTSS
//////// Fuses: SSSH16K,SSSH8K,SSSH4K,SSSS16K,SSSS8K,SSSS4K,NOSSS,RSS4096
//////// Fuses: RSS2048,RSS256,NORSS,PROTECT_HIGH,PROTECT,NOPROTECT,FRC
//////// Fuses: FRC_PLL,PR,PR_PLL,SOSC,LPRC,FRC_DIV_BY_16,FRC_PS,NOIESO,IESO
//////// Fuses: EC,XT,HS,NOPR,OSCIO,NOOSCIO,NOIOL1WAY,IOL1WAY,CKSFSM
//////// Fuses: CKSNOFSM,NOCKSFSM,WPOSTS1,WPOSTS2,WPOSTS3,WPOSTS4,WPOSTS5
//////// Fuses: WPOSTS6,WPOSTS7,WPOSTS8,WPOSTS9,WPOSTS10,WPOSTS11,WPOSTS12
//////// Fuses: WPOSTS13,WPOSTS14,WPOSTS15,WPOSTS16,WPRES32,WPRES128
//////// Fuses: NOWINDIS,WINDIS,NOWDT,WDT,NOPUT,PUT2,PUT4,PUT8,PUT16,PUT32
//////// Fuses: PUT64,PUT128,NOALTI2C,ALTI2C,LPOL_LOW,LPOL_HIGH,HPOL_LOW
//////// Fuses: HPOL_HIGH,PWMPIN,NOPWMPIN,ICSP3,ICSP2,ICSP1,NOJTAG,JTAG
//////// Fuses: DEBUG,NODEBUG
////////
////////////////////////////////////////////////////////////////// I/O
// Discrete I/O Functions: SET_TRIS_x(), OUTPUT_x(), INPUT_x(),
// SET_PULLUP(), INPUT(),
// OUTPUT_LOW(), OUTPUT_HIGH(),
// OUTPUT_FLOAT(), OUTPUT_BIT()
// Constants used to identify pins in the above are:

#define PIN_A0 5648
#define PIN_A1 5649
#define PIN_A2 5650
#define PIN_A3 5651
#define PIN_A4 5652
#define PIN_A7 5655
#define PIN_A8 5656
#define PIN_A9 5657
#define PIN_A10 5658

#define PIN_B0 5712
#define PIN_B1 5713
#define PIN_B2 5714
#define PIN_B3 5715
#define PIN_B4 5716
#define PIN_B5 5717
#define PIN_B6 5718
#define PIN_B7 5719
#define PIN_B8 5720
#define PIN_B9 5721
#define PIN_B10 5722
#define PIN_B11 5723
#define PIN_B12 5724
#define PIN_B13 5725
#define PIN_B14 5726
#define PIN_B15 5727

#define PIN_C0 5776
#define PIN_C1 5777
#define PIN_C2 5778
#define PIN_C3 5779
#define PIN_C4 5780
#define PIN_C5 5781
#define PIN_C6 5782
#define PIN_C7 5783
#define PIN_C8 5784
#define PIN_C9 5785

////////////////////////////////////////////////////////////////// Useful defines
#define FALSE 0
#define TRUE 1

#define BYTE unsigned int8
#define BOOLEAN int1

#define getc getch
#define fgetc getch
#define getchar getch
#define putc putchar
#define fputc putchar
#define fgets gets
#define fputs puts

////////////////////////////////////////////////////////////////// UART
// Constants used in setup_uart() are:
// FALSE - Turn UART off
// TRUE - Turn UART on
#define UART_ADDRESS 2
#define UART_DATA 4
#define UART_AUTODETECT 8
#define UART_AUTODETECT_NOWAIT 9
#define UART_WAKEUP_ON_RDA 10
#define UART_SEND_BREAK 13


////////////////////////////////////////////////////////////////// WDT
// Watch Dog Timer Functions: SETUP_WDT() and RESTART_WDT()
//
// Constants used for SETUP_WDT() are:
#define WDT_ON 1
#define WDT_OFF 0

////////////////////////////////////////////////////////////////// Control
// Control Functions: RESET_CPU(), SLEEP(), RESTART_CAUSE()
// Constants passed into RESTART_CAUSE() are:
#define RESTART_POWER_UP 0
#define RESTART_BROWNOUT 1
#define RESTART_WATCHDOG 4
#define RESTART_SOFTWARE 6
#define RESTART_MCLR 7
#define RESTART_ILLEGAL_OP 14
#define RESTART_TRAP_CONFLICT 15
//
// Constants passed into SLEEP() are:
#define SLEEP_FULL 0 // Default
#define SLEEP_IDLE 1 // Clock and peripherals don't stop

////////////////////////////////////////////////////////////////// INTERNAL RC
// Constants used in setup_oscillator() are:
#define OSC_INTERNAL 32
#define OSC_CRYSTAL 1
#define OSC_CLOCK 2
#define OSC_RC 3
#define OSC_SECONDARY 16

////////////////////////////////////////////////////////////////// Timer
// Timer Functions: SETUP_TIMERx, GET_TIMERx, GET_TIMERxy,
// SET_TIMERx, SET_TIMERxy
// Constants used for SETUP_TIMERx() are:
// (or (via |) together constants from each group)
#define TMR_DISABLED 0x0000
#define TMR_INTERNAL 0xA000
#define TMR_EXTERNAL 0xA002
#define TMR_GATE 0x0040
#define T1_EXTERNAL_SYNC 0xA006 //This only applies to Timer1
#define T1_EXTERNAL_RTC 0xC002 //This only applies to Timer1

#define TMR_DIV_BY_1 0x0000
#define TMR_DIV_BY_8 0x0010
#define TMR_DIV_BY_64 0x0020
#define TMR_DIV_BY_256 0x0030
#define TMR_32_BIT 0x0008 // Only for even numbered timers

/////////////////////////////////////////////////////////// INPUT CAPTURE
// Functions: SETUP_CAPTURE, GET_CAPTURE,
//
// Constants used for SETUP_CAPTURE() are:
#define CAPTURE_OFF 0x0000 // Capture OFF
#define CAPTURE_EE 0x0001 // Capture Every Edge
#define CAPTURE_FE 0x0002 // Capture Falling Edge
#define CAPTURE_RE 0x0003 // Capture Rising Edge
#define CAPTURE_DIV_4 0x0004 // Capture Every 4th Rising Edge
#define CAPTURE_DIV_16 0x0005 // Capture Every 16th Rising Edge
#define CAPTURE_INTERRUPT_ONLY 0x0007 // Interrupt on Rising Edge when in Sleep or Idle

// The following defines can be ORed | with above to configure interrupts
#define INTERRUPT_EVERY_CAPTURE 0x0000 // Interrupt on every capture event
#define INTERRUPT_SECOND_CAPTURE 0x0020 // Interrupt on every second capture event
#define INTERRUPT_THIRD_CAPTURE 0x0040 // Interrupt on every third capture event
#define INTERRUPT_FOURTH_CAPTURE 0x0060 // Interrupt on every fourth capture event

// The following defines can be ORed | with above to select timer
#define CAPTURE_TIMER2 0x0080 // On capture event Timer 2 is captured
#define CAPTURE_TIMER3 0x0000 // On capture event Timer 3 is captured

// The following defines can be ORed | with above to select idle operation mode
#define CAPTURE_HALT_IDLE 0x2000 // Capture module halts during idle mode
#define CAPTURE_CONTINUE_IDLE 0x0000 // Capture module continues during idle mode

/////////////////////////////////////////////////////////// OUTPUT COMPARE
// Functions: SETUP_COMPARE, SET_PWM_DUTY, SET_COMPARE_TIME
//
// Constants used for SETUP_COMPARE() are:
#define COMPARE_OFF 0x0000 // Compare OFF
#define COMPARE_SET_ON_MATCH 0x0001 // Pin from low to high on match
#define COMPARE_CLR_ON_MATCH 0x0002 // Pin from high to low on match
#define COMPARE_TOGGEL 0x0003 // Pin will toggle on every match occurrence
#define COMPARE_SINGLE_PULSE 0x0004 // Pin will generate single pulse on first match
#define COMPARE_CONT_PULSE 0x0005 // Pin will pulse for every match
#define COMPARE_PWM 0x0006 // Compare operates as PWM with fault pin disabled
#define COMPARE_PWM_FAULT 0x0007 // Compare operates as PWM with fault pin enabled

// The following defines can be ORed | with above to select timer
#define COMPARE_TIMER2 0x0000 // Timer 2 is the base timer
#define COMPARE_TIMER3 0x0008 // Timer 3 is the base timer

// The following defines can be ORed | with above to select idle operation mode
#define COMPARE_HALT_IDLE 0x2000 // Compare module halts during idle mode
#define COMPARE_CONTINUE_IDLE 0x0000 // Compare module continues during idle mode

////////////////////////////////////////////////////////////////// SPI
// SPI Functions: SETUP_SPI, SPI_WRITE, SPI_READ, SPI_DATA_IN
//
// Constants used in SETUP_SPI() are:
// (or (via |) together constants from each group)
#define SPI_MASTER 0x0020
#define SPI_SLAVE 0x0000

#define SPI_SCK_IDLE_HIGH 0x0040
#define SPI_SCK_IDLE_LOW 0x0000

#define SPI_XMIT_L_TO_H 0x0100
#define SPI_XMIT_H_TO_L 0x0000

#define SPI_MODE_16B 0x0400
#define SPI_MODE_8B 0x0000

#define SPI_SAMPLE_AT_END 0x0200
#define SPI_SAMPLE_AT_MIDDLE 0x0000

#define SPI_SS_ENABLED 0x0000
#define SPI_SS_DISABLED 0x0080

//or (via |) one of the following when operating as MASTER
#define SPI_CLK_DIV_1 0x001F
#define SPI_CLK_DIV_2 0x001B
#define SPI_CLK_DIV_3 0x0017
#define SPI_CLK_DIV_4 0x001E
#define SPI_CLK_DIV_5 0x000F
#define SPI_CLK_DIV_6 0x000B
#define SPI_CLK_DIV_7 0x0007
#define SPI_CLK_DIV_8 0x0003
#define SPI_CLK_DIV_12 0x0016
#define SPI_CLK_DIV_16 0x001D
#define SPI_CLK_DIV_20 0x000E
#define SPI_CLK_DIV_24 0x000A
#define SPI_CLK_DIV_28 0x0006
#define SPI_CLK_DIV_32 0x0002
#define SPI_CLK_DIV_48 0x0015
#define SPI_CLK_DIV_64 0x001C
#define SPI_CLK_DIV_80 0x000D
#define SPI_CLK_DIV_96 0x0009
#define SPI_CLK_DIV_112 0x0005
#define SPI_CLK_DIV_128 0x0001
#define SPI_CLK_DIV_192 0x0014
#define SPI_CLK_DIV_256 0x0010
#define SPI_CLK_DIV_320 0x000C
#define SPI_CLK_DIV_384 0x0008
#define SPI_CLK_DIV_448 0x0004
#define SPI_CLK_DIV_512 0x0000

//The following defines are provided for compatibility
#define SPI_L_TO_H SPI_SCK_IDLE_LOW
#define SPI_H_TO_L SPI_SCK_IDLE_HIGH

////////////////////////////////////////////////////////////////// ADC
// ADC Functions: SETUP_ADC(), SETUP_ADC_PORTS()
// SET_ADC_CHANNEL(), READ_ADC()
//
// Constants used for SETUP_ADC() are:
// Clock is at ADCS<5:0> of ADCON3 Reg. (0x02A4)
// Tad = (Tcy/2)*(ADCS<5:0>+1)
#define ADC_OFF 0x10000
#define ADC_CLOCK 0x0000 // External
#define ADC_CLOCK_DIV_2 0x0001
#define ADC_CLOCK_DIV_4 0x0003
#define ADC_CLOCK_DIV_8 0x0007
#define ADC_CLOCK_DIV_16 0x000F
#define ADC_CLOCK_DIV_32 0x001F
#define ADC_CLOCK_DIV_64 0x003F
#define ADC_CLOCK_INTERNAL 0x8000 // Internal

// The following may be OR'ed in with the above using |
// Auto-Sample Time bits
#define ADC_TAD_MUL_0 0x0000
#define ADC_TAD_MUL_2 0x0200
#define ADC_TAD_MUL_4 0x0400
#define ADC_TAD_MUL_8 0x0800
#define ADC_TAD_MUL_16 0x1000
#define ADC_TAD_MUL_31 0x1F00

// Constants used in READ_ADC() are:
#define ADC_START_AND_READ 0x07
#define ADC_START_ONLY 0x01
#define ADC_READ_ONLY 0x06



// Constants used in SETUP_ADC_PORTS() are:
// First argument:
// OR together desired pins
#define NO_ANALOGS 0 // None
#define ALL_ANALOG 0xFFFFFFFF // All
#define sAN0 0x00000001 //| A1
#define sAN1 0x00000002 //| A2
#define sAN2 0x00000004 //| B0
#define sAN3 0x00000008 //| B1
#define sAN4 0x00000010 //| B2
#define sAN5 0x00000020 //| 3
#define sAN6 0x00000040 //| C0
#define sAN7 0x00000080 //| C1
#define sAN8 0x00000100 //| 2
#define sAN9 0x00000200 //| B15
#define sAN10 0x00000400 //| B13
#define sAN11 0x00000800 //| B14
#define sAN12 0x00001000 //| 12

// Optional Second argument:
#define VSS_VDD 0x0000 // Range 0-Vdd
#define VREF_VREF 0x6000 // Range VrefL-VrefH
#define VREF_VDD 0x4000 // Range VrefL-Vdd
#define VSS_VREF 0x2000 // Range 0-VrefH

////////////////////////////////////////////////////////////////// COMP
// Comparator Variables: C1OUT, C2OUT
// Constants used in setup_comparator() are:
#define NC_NC_NC_NC 0x00
#define A4_A5_NC_NC 0x201
#define A4_VR_NC_NC 0x200
#define A5_VR_NC_NC 0x202
#define NC_NC_A2_A3 0x804
#define NC_NC_A2_VR 0x800
#define NC_NC_A3_VR 0x808
#define A4_A5_A2_A3 A4_A5_NC_NC | NC_NC_A2_A3
#define A4_VR_A2_VR A4_VR_NC_NC | NC_NC_A2_VR
#define A5_VR_A3_VR A5_VR_NC_NC | NC_NC_A3_VR

#define C1_INVERT 0x10
#define C2_INVERT 0x20
#define C1_OUTPUT 0x40
#define C2_OUTPUT 0x80

//#bit COMPARATOR1_RESULT = getenv("SFR:CMCON").6
//#bit COMPARATOR2_RESULT = getenv("SFR:CMCON").7

////////////////////////////////////////////////////////////////// PMP
// SPI Functions: setup_pmp(), pmp_address(), psp_read(), pmp_read(),
// psp_write(), pmp_write(), psp_output_full(),psp_input_full(),
// psp_overflow(), pmp_output_full(), pmp_input_full(),
// pmp_overflow()
// Constants used in SETUP_PMP() and SETUP_PSP() are:
#define PAR_ENABLE 0x8000
#define PAR_DISABLE 0x0000 // Module enable/disable options
#define PAR_STOP_IN_IDLE 0x2000
#define PAR_CONTINUE_IN_IDLE 0x0000
#define PAR_ADDR_NOT_MULTIPLEXED 0x0000 // Address multiplexing options
#define PAR_LOW_ADDR_MULTIPLEXED 0x0800 // Address multiplexing options
#define PAR_FULL_ADDR_MULTIPLEXED 0x1000 // Address multiplexing options
#define PAR_PTBEEN_ENABLE 0x0400 // Byte Enable Port Enable bit
#define PAR_PTWREN_ENABLE 0x0200 // Write Enable Strobe bit
#define PAR_PTRDEN_ENABLE 0x0100 // Read/Write Strobe Port bit
#define PAR_ALP_ACTIVE_HIGH 0x0020 // Address latch polarity high
#define PAR_BEP_ACTIVE_HIGH 0x0004 // Byte Enable Polarity
#define PAR_WRSP_ACTIVE_HIGH 0x0002 // Write strobe Polarity bit
#define PAR_RDSP_ACTIVE_HIGH 0x0001 // Read strobe Polarity bit
#define PAR_CS_XX 0x0000 // Chip select pins used for address
#define PAR_CS_X1 0x0008 // Chip select pin 1 used, active high
#define PAR_CS_X0 0x0000 // Chip select pin 1 used, active low
#define PAR_CS_1X 0x0050 // Chip select pin 2 used, active high
#define PAR_CS_0X 0x0040 // Chip select pin 2 used, active low
#define PAR_CS_00 0x0080 // Chip select pins 1,2 used, active low
#define PAR_CS_11 0x0098 // Chip select pins 1,2 used, active high
#define PAR_CS_10 0x0090 // Chip select pins 1,2 used, 1 is active low, 2 is high
#define PAR_CS_01 0x0088 // Chip select pins 1,2 used, 1 is active high, 2 is low
#define PAR_INTR_ON_RW 0x20000000 // Interrupt on read write
#define PAR_NO_INTR_STALL_ACTIVATED 0x40000000 // No interrupt, processor stall activated
#define PAR_INTR_ON_3_RW_BUF 0x60000000 // Interrupt on write to Buffer 3 or read from Buffer 3
#define PAR_PSP_AUTO_INC 0x18000000 // Read write buffers auto increment
#define PAR_DEC_ADDR 0x10000000 // Increment the address
#define PAR_INC_ADDR 0x08000000 // Decrement the address
#define PAR_MASTER_MODE_1 0x03000000 // Master mode 1
#define PAR_MASTER_MODE_2 0x02000000 // Master mode 2
#define PAR_WAITB1 0x00000000 // 1 Tcy Wait state for data setup R/W
#define PAR_WAITB2 0x00400000 // 2 Tcy Wait state for data setup R/W
#define PAR_WAITB3 0x00800000 // 3 Tcy Wait state for data setup R/W
#define PAR_WAITB4 0x00C00000 // 4 Tcy Wait state for data setup R/W
#define PAR_WAITM0 0x00000000 // 0 wait state for Read to byte
#define PAR_WAITM1 0x00040000 // 1 Tcy wait state for Read to byte
#define PAR_WAITM2 0x00080000 // 2 Tcy wait state for Read to byte
#define PAR_WAITM3 0x000C0000 // 3 Tcy wait state for Read to byte
#define PAR_WAITM15 0x003C0000 // 15 wait states
#define PAR_WAITE1 0x00000000 // 1 Tcy Wait for data hold after strobe
#define PAR_WAITE2 0x00010000 // 2 Tcy Wait for data hold after strobe
#define PAR_WAITE3 0x00020000 // 3 Tcy Wait for data hold after strobe
#define PAR_WAITE4 0x00030000 // 4 Tcy Wait for data hold after strobe

////////////////////////////////////////////////////////////////// CRC
// CRC Functions: setup_crc(), crc_init(), crc_calc(), crc_calc8()
//

////////////////////////////////////////////////////////////////// RTC
// RTC Functions: setup_rtc(), setup_rtc_alarm(), rtc_read(),
// rtc_write(), rtc_alarm_read(), rtc_alarm_write()
// Structure used in read and write functions (pass pointer):
typedef struct {
int8 tm_year;
int8 tm_yday; // Not used by built in functions
int8 tm_mday;
int8 tm_mon;
int8 tm_hour;
int8 tm_wday;
int8 tm_sec;
int8 tm_min;
int8 tm_isdst; // Not used by built in functions
} rtc_time_t;
//
// Constants used in setup_rtc() are: // Second param is calibration
#define RTC_ENABLE 0x8000
#define RTC_DISABLE 0
#define RTC_OUTPUT_SECONDS 0x20400
#define RTC_OUTPUT_ALARM 0x00400
//
// Constants used in setup_rtc_alarm() first param are:
#define RTC_ALARM_ENABLE 0x8000
#define RTC_ALARM_DISABLE 0
#define RTC_CHIME_ENABLE 0x4000
#define RTC_CHIME_DISABLE 0
// Constants used in setup_rtc_alarm() second param are: // Third param is repeat#
#define RTC_ALARM_HALFSECOND 0x0000
#define RTC_ALARM_SECOND 0x0400
#define RTC_ALARM_10_SECONDS 0x0800
#define RTC_ALARM_MINUTE 0x0C00
#define RTC_ALARM_10_MINUTES 0x1000
#define RTC_ALARM_HOUR 0x1400
#define RTC_ALARM_DAY 0x1800
#define RTC_ALARM_WEEK 0x1C00
#define RTC_ALARM_MONTH 0x2000
#define RTC_ALARM_YEAR 0x2400

////////////////////////////////////////////////////////////////// QEI
// QEI Functions: setup_qei(), qet_set_count(), qei_get_count(),
// qei_status()
//
// Constants used in setup_qei() first param are:
#define QEI_DISABLED 0
#define QEI_MODE_X2 0x0400
#define QEI_MODE_X4 0x0600
#define QEI_MODE_TIMER 0x0100
#define QEI_STOP_WHEN_IDLE 0x2000
#define QEI_SWAP_AB 0x0080
#define QEI_OUTPUT_ENABLE 0x0040
#define QEI_RESET_WHEN_MAXCOUNT 0x0100
#define QEI_RESET_WHEN_IDX_PULSE 0x0004
#define QEI_TIMER_GATED 0x0020
#define QEI_TIMER_INTERNAL 0x0000
#define QEI_TIMER_EXTERNAL 0x0002
#define QEI_TIMER_DIV_BY_1 0x0000
#define QEI_TIMER_DIV_BY_8 0x0008
#define QEI_TIMER_DIV_BY_64 0x0010
#define QEI_TIMER_DIV_BY_256 0x0018
// Constants used in setup_qei() second param are: // Third param is MAXCOUNT
#define QEI_FILTER_DIV_1 0x0000
#define QEI_FILTER_DIV_2 0x0010
#define QEI_FILTER_DIV_4 0x0020
#define QEI_FILTER_DIV_16 0x0030
#define QEI_FILTER_DIV_32 0x0040
#define QEI_FILTER_DIV_64 0x0050
#define QEI_FILTER_DIV_128 0x0060
#define QEI_FILTER_DIV_256 0x0070
#define QEI_FILTER_OUTPUT 0x0080
#define QEI_NO_ERROR_INTS 0x0100
#define QEI_IDX_WHEN_A0 0x0000 // for 2X mode
#define QEI_IDX_WHEN_A1 0x0200 // for 2X mode
#define QEI_IDX_WHEN_B0 0x0400 // for 2X mode
#define QEI_IDX_WHEN_B1 0x0600 // for 2X mode
#define QEI_IDX_WHEN_A0_B0 0x0000 // for 4X mode
#define QEI_IDX_WHEN_A1_B0 0x0200 // for 4X mode
#define QEI_IDX_WHEN_A0_B1 0x0400 // for 4X mode
#define QEI_IDX_WHEN_A1_B1 0x0600 // for 4X mode
// Constants returned from qei_status() are:
#define QEI_POS_ERROR 0x8000
#define QEI_FORWARD 0x0800
#define QEI_INDEX_PIN 0x1000

////////////////////////////////////////////////////////////////// MOTOR PWM
// MPWM Functions: setup_motor_pwm(), set_motor_pwm_unit(),
// set_motor_pwm_duty(), set_motor_pwm_event(),
// get_motor_pwm_count()
// Constants used in setup_motor_pwm() second param are (first param is unit number 1,2...):
#define MPWM_DISABLED 0
#define MPWM_FREE_RUN 0x8000
#define MPWM_SINGLE_PULSE 0x8001
#define MPWM_UP_DOWN 0x8002
#define MPWM_UP_DOWN_WITH_INTS 0x8003
// OR in any of the following:
#define MPWM_HALT_WHEN_IDLE 0x2000
#define MPWM_DUTY_UPDATES_IMMEADIATE 0x40000
#define MPWM_SYNC_OVERRIDES 0x20000
#define MPWM_DISABLE_UPDATES 0x10000
#define MPWM_LATCH_FAULTS 0x100000

// Constants used in set_motor_unit() third param are: (first param is unit number 1,2... and second param is pwm pin pair 1,2,3 or 4)
#define MPWM_INDEPENDENT 0x0001
#define MPWM_ENABLE 0x0006 // both H and L
#define MPWM_ENABLE_H 0x0004
#define MPWM_ENABLE_L 0x0002

#define MPWM_FORCE_L_0 0x0010
#define MPWM_FORCE_L_1 0x0050
#define MPWM_FORCE_H_0 0x0020
#define MPWM_FORCE_H_1 0x00A0

#define MPWM_FAULTA_LA_HA 0x0700
#define MPWM_FAULTA_LA_HI 0x0500
#define MPWM_FAULTA_LI_HA 0x0600
#define MPWM_FAULTA_LI_HI 0x0400
#define MPWM_FAULTB_LA_HA 0x7000
#define MPWM_FAULTB_LA_HI 0x5000
#define MPWM_FAULTB_LI_HA 0x6000
#define MPWM_FAULTB_LI_HI 0x4000
#define MPWM_FAULT_NO_CHANGE 0x0000

////////////////////////////////////////////////////////////////// DCI
// DCI Functions: setup_dci(), dci_start(), dci_read(), dci_write(),
// , dci_data_received(), dci_transmit_ready()
//
#define MULTICHANNEL_MODE 0x0000
#define I2S_MODE 0x0001
#define AC97_16BIT_MODE 0x0002
#define AC97_20BIT_MODE 0x0003

#define JUSTIFY_DATA 0x0020 //Start data transmission on the same clock cycle as COFS pulses (multichannel)
#define MULTI_DEVICE_BUS 0x0040 //Tri-states the CSDO pin during unused time slots, normally drives '0'

#define UNDERFLOW_LAST 0x0080 //Transmits the last written value to the dci when data underflow occurs. Default is undeflow silence.
#define UNDERFLOW_SILENCE 0x0000 //Transmit '0's on data undeflow. This will cause a clicking noise if you are underflowing data while outputing to a codec.

#define DCI_SLAVE 0x0100 //Default is master
#define DCI_MASTER 0x0000

#define SAMPLE_FALLING_EDGE 0x0000 //Default is Sample on the rising edge of the clock
#define SAMPLE_RISING_EDGE 0x0200

#define DCI_CLOCK_INPUT 0x0400 //SCLK is an input (supplied by codec or external source)
#define DCI_CLOCK_OUTPUT 0x0000 //Default is clock output

#define ENABLE_LOOPBACK 0x0800 //Connect the CSDI/CSDO internally; loops all of the sound back onto the bus

#define CODEC_MULTICHANNEL 0x0000 //enables multichannel (generic) codec support
#define CODEC_I2S 0x0001 //enables the I2S protocol
#define CODEC_AC16 0x0002 //enables the AC-16 protocol, setupCodecTransmission has no effect
#define CODEC_AC20 0x0003 //enables the AC-20 protocol, setupCodecTransmission has no effect

#define BUS_MASTER 0x0000 //designates this device as the bus master
#define BUS_SLAVE 0x0300 //designates this device as a slave on a bus controlled by another codec

#define TRISTATE_BUS 0x0040 //when in master mode, the module will be in high impedance
//during disabled frames (default drives 0's onto bus)
#define SYNC_COFS_DATA_PULSE 0x0020 //signifies that data starts transmitting on the same SCK pulse as the edge of the COFS pulse
//(default data starts on the clock after the rising edge of COFS
/* Determines when a sample is taken */
#define SAMPLE_RISING 0x0200 //sample data on the rising edge of the clock
#define SAMPLE_FALLING 0x0000 //sample data on the falling edge of the clock

#define DCI_4BIT_WORD 0x0003
#define DCI_5BIT_WORD 0x0004
#define DCI_6BIT_WORD 0x0005
#define DCI_7BIT_WORD 0x0006
#define DCI_8BIT_WORD 0x0007
#define DCI_9BIT_WORD 0x0008
#define DCI_10BIT_WORD 0x0009
#define DCI_11BIT_WORD 0x000A
#define DCI_12BIT_WORD 0x000B
#define DCI_13BIT_WORD 0x000C
#define DCI_14BIT_WORD 0x000D
#define DCI_15BIT_WORD 0x000E
#define DCI_16BIT_WORD 0x000F

#define DCI_1WORD_FRAME 0x0000
#define DCI_2WORD_FRAME 0x0010 << 1
#define DCI_3WORD_FRAME 0x0020 << 1
#define DCI_4WORD_FRAME 0x0030 << 1
#define DCI_5WORD_FRAME 0x0040 << 1
#define DCI_6WORD_FRAME 0x0050 << 1
#define DCI_7WORD_FRAME 0x0060 << 1
#define DCI_8WORD_FRAME 0x0070 << 1
#define DCI_9WORD_FRAME 0x0080 << 1
#define DCI_10WORD_FRAME 0x0090 << 1
#define DCI_11WORD_FRAME 0x00A0 << 1
#define DCI_12WORD_FRAME 0x00B0 << 1
#define DCI_13WORD_FRAME 0x00C0 << 1
#define DCI_14WORD_FRAME 0x00D0 << 1
#define DCI_15WORD_FRAME 0x00E0 << 1
#define DCI_16WORD_FRAME 0x00F0 << 1

#define DCI_1WORD_INTERRUPT 0x0000
#define DCI_2WORD_INTERRUPT 0x0400
#define DCI_3WORD_INTERRUPT 0x0800
#define DCI_4WORD_INTERRUPT 0x0C00

#define RECEIVE_NONE 0x0000
#define RECEIVE_ALL 0xFFFF
#define RECEIVE_SLOT0 0x0001
#define RECEIVE_SLOT1 0x0002
#define RECEIVE_SLOT2 0x0004
#define RECEIVE_SLOT3 0x0008
#define RECEIVE_SLOT4 0x0010
#define RECEIVE_SLOT5 0x0020
#define RECEIVE_SLOT6 0x0040
#define RECEIVE_SLOT7 0x0080
#define RECEIVE_SLOT8 0x0100
#define RECEIVE_SLOT9 0x0200
#define RECEIVE_SLOT10 0x0400
#define RECEIVE_SLOT11 0x0800
#define RECEIVE_SLOT12 0x1000
#define RECEIVE_SLOT13 0x2000
#define RECEIVE_SLOT14 0x4000
#define RECEIVE_SLOT15 0x8000

#define TRANSMIT_NONE 0x0000
#define TRANSMIT_ALL 0xFFFF
#define TRANSMIT_SLOT0 0x0001
#define TRANSMIT_SLOT1 0x0002
#define TRANSMIT_SLOT2 0x0004
#define TRANSMIT_SLOT3 0x0008
#define TRANSMIT_SLOT4 0x0010
#define TRANSMIT_SLOT5 0x0020
#define TRANSMIT_SLOT6 0x0040
#define TRANSMIT_SLOT7 0x0080
#define TRANSMIT_SLOT8 0x0100
#define TRANSMIT_SLOT9 0x0200
#define TRANSMIT_SLOT10 0x0400
#define TRANSMIT_SLOT11 0x0800
#define TRANSMIT_SLOT12 0x1000
#define TRANSMIT_SLOT13 0x2000
#define TRANSMIT_SLOT14 0x4000
#define TRANSMIT_SLOT15 0x8000


////////////////////////////////////////////////////////////////// DMA
// DMA Functions: setup_dma(), dma_start(), dma_status()
//
// Constants used in setup_dma() second param are:

#define DMA_IN_SPI1 (0x0A0000|getenv("sfr:SPI1BUF"))
#define DMA_OUT_SPI1 (0x8A0000|getenv("sfr:SPI1BUF"))
#define DMA_IN_SPI2 (0x210000|getenv("sfr:SPI2BUF"))
#define DMA_OUT_SPI2 (0xA10000|getenv("sfr:SPI2BUF"))
#define DMA_IN_UART1 (0x0B0000|getenv("sfr:U1RXREG"))
#define DMA_OUT_UART1 (0x8C0000|getenv("sfr:U1TXREG"))
#define DMA_IN_UART2 (0x1E0000|getenv("sfr:U2RXREG"))
#define DMA_OUT_UART2 (0x9F0000|getenv("sfr:U2TXREG"))
#define DMA_IN_ADC1 (0x0D0000|getenv("sfr:ADC1BUF0"))
////////////////////////////////////////////////////////////////// DAC
// Digital to Analog Functions: SETUP_DAC(), DAC_WRITE()
// Constants used in SETUP_DAC() are:
#define DAC_OFF 0
#define DAC_RIGHT_ON 0x00808000
#define DAC_LEFT_ON 0x80008000
#define DAC_RIGHT_MIDPOINT 0x00A08000
#define DAC_LEFT_MIDPOINT 0xA0008000
#define DAC_SIGNED 0x100
#define DAC_SLEEP_ON 0x1000
#define DAC_IDLE_OFF 0x2000
// Constants used as the first param in DAC_WRITE() are:
#define DAC_DEFAULT 0
#define DAC_RIGHT 1
#define DAC_LEFT 2


#define DMA_IN_ECAN1 (0x220000|getenv("sfr:C1RXD"))
#define DMA_OUT_ECAN1 (0xC60000|getenv("sfr:C1TXD"))
#define DMA_INT0 0x000000 // or in direction and perif address
#define DMA_IC1 0x010000 // or in direction and perif address
#define DMA_IC2 0x050000 // or in direction and perif address
#define DMA_OC1 0x020000 // or in direction and perif address
#define DMA_OC2 0x060000 // or in direction and perif address
#define DMA_TIMER2 0x070000 // or in direction and perif address
#define DMA_TIMER3 0x080000 // or in direction and perif address
#define DMA_OUT_DCI (0xBC0000|getenv("sfr:TXBUF0"))
#define DMA_IN_DCI (0x3C0000|getenv("sfr:RXBUF0"))
#define DMA_OUT_DACR (0xCE0000|getenv("sfr:DAC1RDAT"))
#define DMA_OUT_DACL (0xCF0000|getenv("sfr:DAC1LDAT"))
#define DMA_IN 0x00
#define DMA_OUT 0x800000
// Constants used in setup_dma() third param are:
#define DMA_BYTE 0x40
#define DMA_WORD 0x00 // default
#define DMA_HALF_INT 0x10 // interrupt when half full
#define DMA_WRITE_NULL 0x08
// Constants used in dma_start() second param are:
#define DMA_CONTINOUS 0x00
#define DMA_ONE_SHOT 0x01
#define DMA_PING_PONG 0x02
#define DMA_NO_INC 0x10
#define DMA_PERIF_ADDR 0x20 // Device supplies address
#define DMA_FORCE_NOW 0x100
// Constants returned from dma_status() are:
#define DMA_IN_ERROR 0x01
#define DMA_OUT_ERROR 0x02
#define DMA_B_SELECT 0x04

////////////////////////////////////////////////////////////////// INT
// Interrupt Functions: ENABLE_INTERRUPTS(), DISABLE_INTERRUPTS(),
// CLEAR_INTERRUPT(), INTERRUPT_ACTIVE(),
// EXT_INT_EDGE()
//
// Constants used in EXT_INT_EDGE() are:
#define L_TO_H 0x40
#define H_TO_L 0
//
// Constants used in other interrupt functions are:
#define INTR_GLOBAL 0x400
#define INTR_NORMAL 0x100
#define INTR_ALTERNATE 0x200
#define INTR_LEVEL0 0x500
#define INTR_LEVEL1 0x501
#define INTR_LEVEL2 0x502
#define INTR_LEVEL3 0x503
#define INTR_LEVEL4 0x504
#define INTR_LEVEL5 0x505
#define INTR_LEVEL6 0x506
#define INTR_LEVEL7 0x507

#define INTR_CN_PIN 0x8000 // or in a PIN_xx constant

#define INT_OSCFAIL 1
#define INT_ADDRERR 2
#define INT_STACKERR 3
#define INT_MATHERR 4
#define INT_DMAERR 5
#define INT_EXT0 6
#define INT_IC1 7
#define INT_OC1 8
#define INT_TIMER1 9
#define INT_DMA0 69
#define INT_IC2 70
#define INT_OC2 71
#define INT_TIMER2 72
#define INT_TIMER3 73
#define INT_SPI1E 74
#define INT_SPI1 75
#define INT_RDA 76
#define INT_TBE 77
#define INT_ADC1 78
#define INT_DMA1 79
#define INT_SI2C 81
#define INT_MI2C 82
#define INT_CNI 84
#define INT_EXT1 85
#define INT_IC7 87
#define INT_IC8 88
#define INT_DMA2 89
#define INT_OC3 90
#define INT_OC4 91
#define INT_TIMER4 92
#define INT_TIMER5 93
#define INT_EXT2 94
#define INT_RDA2 95
#define INT_TBE2 96
#define INT_SPI2E 97
#define INT_SPI2 98
#define INT_C1RX 99
#define INT_CAN1 100
#define INT_DMA3 101
#define INT_PWM1 110
#define INT_DMA4 111
#define INT_QEI 123
#define INT_DMA5 126
#define INT_PWM2 127
#define INT_FAULTA 128
#define INT_UART1E 130
#define INT_UART2E 131
#define INT_QEI2 132
#define INT_DMA6 133
#define INT_DMA7 134
#define INT_C1TX 135
#define INT_FAULTA2 139
#define INT_COMP 152
#define INT_PMP 164
#define INT_RTC 173
#define INT_CRC 174
#define INT_DAC1R 177
#define INT_DAC1L 178



//********************************
#word WREG0 = 0x000

#word WREG1 = 0x002

#word WREG2 = 0x004

#word WREG3 = 0x006

#word WREG4 = 0x008

#word WREG5 = 0x00A

#word WREG6 = 0x00C

#word WREG7 = 0x00E

#word WREG8 = 0x010

#word WREG9 = 0x012

#word WREG10 = 0x014

#word WREG11 = 0x016

#word WREG12 = 0x018

#word WREG13 = 0x01A

#word WREG14 = 0x01C

#word WREG15 = 0x01E

#word SPLIM = 0x020

#word ACCAL = 0x022

#word ACCAH = 0x024

struct ACCAUBITS {
unsigned int ACCAU0:1;
unsigned int ACCAU1:1;
unsigned int ACCAU2:1;
unsigned int ACCAU3:1;
unsigned int ACCAU4:1;
unsigned int ACCAU5:1;
unsigned int ACCAU6:1;
unsigned int ACCAU7:1;
unsigned int SIGNEXT8:1;
unsigned int SIGNEXT9:1;
unsigned int SIGNEXT10:1;
unsigned int SIGNEXT11:1;
unsigned int SIGNEXT12:1;
unsigned int SIGNEXT13:1;
unsigned int SIGNEXT14:1;
unsigned int SIGNEXT7:1;
} ACCAUbits;
#word ACCAUbits = 0x026
#word ACCAU = 0x026

#word ACCBL = 0x028

#word ACCBH = 0x02A

struct ACCBUBITS {
unsigned int ACCBU0:1;
unsigned int ACCBU1:1;
unsigned int ACCBU2:1;
unsigned int ACCBU3:1;
unsigned int ACCBU4:1;
unsigned int ACCBU5:1;
unsigned int ACCBU6:1;
unsigned int ACCBU7:1;
unsigned int SIGNEXT8:1;
unsigned int SIGNEXT9:1;
unsigned int SIGNEXT10:1;
unsigned int SIGNEXT11:1;
unsigned int SIGNEXT12:1;
unsigned int SIGNEXT13:1;
unsigned int SIGNEXT14:1;
unsigned int SIGNEXT7:1;
} ACCBUbits;
#word ACCBUbits = 0x02C
#word ACCBU = 0x02C

#word PCL = 0x02E

#word PCH = 0x030

#word TBLPAG = 0x032

#word PSVPAG = 0x034

#word RCOUNT = 0x036

#word DCOUNT = 0x038

#word DOSTARTL = 0x03A

#word DOSTARTH = 0x03C

#word DOENDL = 0x03E

#word DOENDH = 0x040

struct SRBITS {
unsigned int C:1;
unsigned int Z:1;
unsigned int OV:1;
unsigned int N:1;
unsigned int RA:1;
unsigned int IPL5:1;
unsigned int IPL6:1;
unsigned int IPL7:1;
unsigned int DC:1;
unsigned int DA:1;
unsigned int SAB:1;
unsigned int OAB:1;
unsigned int SB:1;
unsigned int SA:1;
unsigned int OB:1;
unsigned int OA:1;
} SRbits;
#word SRbits = 0x042
#word SR = 0x042

struct CORCONBITS {
// unsigned int IF:1;
unsigned int RND:1;
unsigned int PSV:1;
unsigned int IPL:1;
unsigned int ACCSAT:1;
unsigned int SATDW:1;
unsigned int SATB:1;
unsigned int SATA:1;
unsigned int DL8:1;
unsigned int DL9:1;
unsigned int DL10:1;
unsigned int EDT:1;
unsigned int US:1;
} CORCONbits;
#word CORCONbits = 0x044
#word CORCON = 0x044

struct MODCONBITS {
unsigned int XWM0:1;
unsigned int XWM1:1;
unsigned int XWM2:1;
unsigned int XWM3:1;
unsigned int YWM4:1;
unsigned int YWM5:1;
unsigned int YWM6:1;
unsigned int YWM7:1;
unsigned int BWM8:1;
unsigned int BWM9:1;
unsigned int BWM10:1;
unsigned int BWM3:1;
unsigned int :2;
unsigned int YMODEN:1;
unsigned int XMODEN:1;
} MODCONbits;
#word MODCONbits = 0x046
#word MODCON = 0x046

#word XMODSRT = 0x048

#word XMODEND = 0x04A

#word YMODSRT = 0x04C

#word YMODEND = 0x04E

struct XBREVBITS {
unsigned int XB0:1;
unsigned int XB1:1;
unsigned int XB2:1;
unsigned int XB3:1;
unsigned int XB4:1;
unsigned int XB5:1;
unsigned int XB6:1;
unsigned int XB7:1;
unsigned int XB8:1;
unsigned int XB9:1;
unsigned int XB10:1;
unsigned int XB11:1;
unsigned int XB12:1;
unsigned int XB13:1;
unsigned int XB14:1;
unsigned int BREN:1;
} XBREVbits;
#word XBREVbits = 0x050
#word XBREV = 0x050

#word DISICNT = 0x052

struct CNEN1BITS {
unsigned int CN0IE:1;
unsigned int CN1IE:1;
unsigned int CN2IE:1;
unsigned int CN3IE:1;
unsigned int CN4IE:1;
unsigned int CN5IE:1;
unsigned int CN6IE:1;
unsigned int CN7IE:1;
unsigned int CN8IE:1;
unsigned int CN9IE:1;
unsigned int CN10IE:1;
unsigned int CN11IE:1;
unsigned int CN12IE:1;
unsigned int CN13IE:1;
unsigned int CN14IE:1;
unsigned int CN15IE:1;
} CNEN1bits;
#word CNEN1bits = 0x060
#word CNEN1 = 0x060

struct CNEN2BITS {
unsigned int CN16IE:1;
unsigned int CN17IE:1;
unsigned int CN18IE:1;
unsigned int CN19IE:1;
unsigned int CN20IE:1;
unsigned int CN21IE:1;
unsigned int CN22IE:1;
unsigned int CN23IE:1;
unsigned int CN24IE:1;
unsigned int CN25IE:1;
unsigned int CN26IE:1;
unsigned int CN27IE:1;
unsigned int CN28IE:1;
unsigned int CN29IE:1;
unsigned int CN30IE:1;
} CNEN2bits;
#word CNEN2bits = 0x062
#word CNEN2 = 0x062

struct CNPU1BITS {
unsigned int CN0PUE:1;
unsigned int CN1PUE:1;
unsigned int CN2PUE:1;
unsigned int CN3PUE:1;
unsigned int CN4PUE:1;
unsigned int CN5PUE:1;
unsigned int CN6PUE:1;
unsigned int CN7PUE:1;
unsigned int CN8PUE:1;
unsigned int CN9PUE:1;
unsigned int CN10PUE:1;
unsigned int CN11PUE:1;
unsigned int CN12PUE:1;
unsigned int CN13PUE:1;
unsigned int CN14PUE:1;
unsigned int CN15PUE:1;
} CNPU1bits;
#word CNPU1bits = 0x068
#word CNPU1 = 0x068

struct CNPU2BITS {
unsigned int CN16PUE:1;
unsigned int CN17PUE:1;
unsigned int CN18PUE:1;
unsigned int CN19PUE:1;
unsigned int CN20PUE:1;
unsigned int CN21PUE:1;
unsigned int CN22PUE:1;
unsigned int CN23PUE:1;
unsigned int CN24PUE:1;
unsigned int CN25PUE:1;
unsigned int CN26PUE:1;
unsigned int CN27PUE:1;
unsigned int CN28PUE:1;
unsigned int CN29PUE:1;
unsigned int CN30PUE:1;
} CNPU2bits;
#word CNPU2bits = 0x06A
#word CNPU2 = 0x06A

struct INTCON1BITS {
unsigned int :1;
unsigned int OSCFAIL:1;
unsigned int STKERR:1;
unsigned int ADDRERR:1;
unsigned int MATHERR:1;
unsigned int DMACERR:1;
unsigned int DIV0ERR:1;
unsigned int SFTACERR:1;
unsigned int COVTE:1;
unsigned int OVBTE:1;
unsigned int OVATE:1;
unsigned int COVBERR:1;
unsigned int COVAERR:1;
unsigned int OVBERR:1;
unsigned int OVAERR:1;
unsigned int NSTDIS:1;
} INTCON1bits;
#word INTCON1bits = 0x080
#word INTCON1 = 0x080

struct INTCON2BITS {
unsigned int INT0EP:1;
unsigned int INT1EP:1;
unsigned int INT2EP:1;
unsigned int :11;
unsigned int DISI:1;
unsigned int ALTIVT:1;
} INTCON2bits;
#word INTCON2bits = 0x082
#word INTCON2 = 0x082

struct IFS0BITS {
unsigned int INT0IF:1;
unsigned int IC1IF:1;
unsigned int OC1IF:1;
unsigned int T1IF:1;
unsigned int DMA0IF:1;
unsigned int IC2IF:1;
unsigned int OC2IF:1;
unsigned int T2IF:1;
unsigned int T3IF:1;
unsigned int SPI1EIF:1;
unsigned int SPI1IF:1;
unsigned int U1RXIF:1;
unsigned int U1TXIF:1;
unsigned int AD1IF:1;
unsigned int DMA1IF:1;
} IFS0bits;
#word IFS0bits = 0x084
#word IFS0 = 0x084

struct IFS1BITS {
unsigned int SI2C1IF:1;
unsigned int MI2C1IF:1;
unsigned int CMIF:1;
unsigned int CNIF:1;
unsigned int INT1IF:1;
unsigned int :1;
unsigned int IC7IF:1;
unsigned int IC8IF:1;
unsigned int DMA2IF:1;
unsigned int OC3IF:1;
unsigned int OC4IF:1;
unsigned int T4IF:1;
unsigned int T5IF:1;
unsigned int INT2IF:1;
unsigned int U2RXIF:1;
unsigned int U2TXIF:1;
} IFS1bits;
#word IFS1bits = 0x086
#word IFS1 = 0x086

struct IFS2BITS {
unsigned int SPI2EIF:1;
unsigned int SPI2IF:1;
unsigned int C1RXIF:1;
unsigned int C1IF:1;
unsigned int DMA3IF:1;
unsigned int :8;
unsigned int PMPIF:1;
unsigned int DMA4IF:1;
} IFS2bits;
#word IFS2bits = 0x088
#word IFS2 = 0x088

struct IFS3BITS {
unsigned int :9;
unsigned int PWM1IF:1;
unsigned int QEI1IF:1;
unsigned int :2;
unsigned int DMA5IF:1;
unsigned int RTCIF:1;
unsigned int FLTA1IF:1;
} IFS3bits;
#word IFS3bits = 0x08A
#word IFS3 = 0x08A

struct IFS4BITS {
unsigned int :1;
unsigned int U1EIF:1;
unsigned int U2EIF:1;
unsigned int CRCIF:1;
unsigned int DMA6IF:1;
unsigned int DMA7IF:1;
unsigned int C1TXIF:1;
unsigned int :2;
unsigned int PWM2IF:1;
unsigned int FLTA2IF:1;
unsigned int QEI2IF:1;
unsigned int :2;
unsigned int DAC1RIF:1;
unsigned int DAC1LIF:1;
} IFS4bits;
#word IFS4bits = 0x08C
#word IFS4 = 0x08C

struct IEC0BITS {
unsigned int INT0IE:1;
unsigned int IC1IE:1;
unsigned int OC1IE:1;
unsigned int T1IE:1;
unsigned int DMA0IE:1;
unsigned int IC2IE:1;
unsigned int OC2IE:1;
unsigned int T2IE:1;
unsigned int T3IE:1;
unsigned int SPI1EIE:1;
unsigned int SPI1IE:1;
unsigned int U1RXIE:1;
unsigned int U1TXIE:1;
unsigned int AD1IE:1;
unsigned int DMA1IE:1;
} IEC0bits;
#word IEC0bits = 0x094
#word IEC0 = 0x094

struct IEC1BITS {
unsigned int SI2C1IE:1;
unsigned int MI2C1IE:1;
unsigned int CMIE:1;
unsigned int CNIE:1;
unsigned int INT1IE:1;
unsigned int :1;
unsigned int IC7IE:1;
unsigned int IC8IE:1;
unsigned int DMA2IE:1;
unsigned int OC3IE:1;
unsigned int OC4IE:1;
unsigned int T4IE:1;
unsigned int T5IE:1;
unsigned int INT2IE:1;
unsigned int U2RXIE:1;
unsigned int U2TXIE:1;
} IEC1bits;
#word IEC1bits = 0x096
#word IEC1 = 0x096

struct IEC2BITS {
unsigned int SPI2EIE:1;
unsigned int SPI2IE:1;
unsigned int C1RXIE:1;
unsigned int C1IE:1;
unsigned int DMA3IE:1;
unsigned int :8;
unsigned int PMPIE:1;
unsigned int DMA4IE:1;
} IEC2bits;
#word IEC2bits = 0x098
#word IEC2 = 0x098

struct IEC3BITS {
unsigned int :9;
unsigned int PWM1IE:1;
unsigned int QEI1IE:1;
unsigned int :2;
unsigned int DMA5IE:1;
unsigned int RTCIE:1;
unsigned int FLTA1IE:1;
} IEC3bits;
#word IEC3bits = 0x09A
#word IEC3 = 0x09A

struct IEC4BITS {
unsigned int :1;
unsigned int U1EIE:1;
unsigned int U2EIE:1;
unsigned int CRCIE:1;
unsigned int DMA6IE:1;
unsigned int DMA7IE:1;
unsigned int C1TXIE:1;
unsigned int :2;
unsigned int PWM2IE:1;
unsigned int FLTA2IE:1;
unsigned int QEI2IE:1;
unsigned int :2;
unsigned int DAC1RIE:1;
unsigned int DAC1LIE:1;
} IEC4bits;
#word IEC4bits = 0x09C
#word IEC4 = 0x09C

struct IPC0BITS {
unsigned int INT0IP0:1;
unsigned int INT0IP1:1;
unsigned int INT0IP2:1;
unsigned int :1;
unsigned int IC1IP4:1;
unsigned int IC1IP5:1;
unsigned int IC1IP2:1;
unsigned int :1;
unsigned int OC1IP8:1;
unsigned int OC1IP9:1;
unsigned int OC1IP2:1;
unsigned int :1;
unsigned int T1IP12:1;
unsigned int T1IP13:1;
unsigned int T1IP2:1;
} IPC0bits;
#word IPC0bits = 0x0A4
#word IPC0 = 0x0A4

struct IPC1BITS {
unsigned int DMA0IP0:1;
unsigned int DMA0IP1:1;
unsigned int DMA0IP2:1;
unsigned int :1;
unsigned int IC2IP4:1;
unsigned int IC2IP5:1;
unsigned int IC2IP2:1;
unsigned int :1;
unsigned int OC2IP8:1;
unsigned int OC2IP9:1;
unsigned int OC2IP2:1;
unsigned int :1;
unsigned int T2IP12:1;
unsigned int T2IP13:1;
unsigned int T2IP2:1;
} IPC1bits;
#word IPC1bits = 0x0A6
#word IPC1 = 0x0A6

struct IPC2BITS {
unsigned int T3IP0:1;
unsigned int T3IP1:1;
unsigned int T3IP2:1;
unsigned int :1;
unsigned int SPI1EIP4:1;
unsigned int SPI1EIP5:1;
unsigned int SPI1EIP2:1;
unsigned int :1;
unsigned int SPI1IP8:1;
unsigned int SPI1IP9:1;
unsigned int SPI1IP2:1;
unsigned int :1;
unsigned int U1RXIP12:1;
unsigned int U1RXIP13:1;
unsigned int U1RXIP2:1;
} IPC2bits;
#word IPC2bits = 0x0A8
#word IPC2 = 0x0A8

struct IPC3BITS {
unsigned int U1TXIP0:1;
unsigned int U1TXIP1:1;
unsigned int U1TXIP2:1;
unsigned int :1;
unsigned int AD1IP4:1;
unsigned int AD1IP5:1;
unsigned int AD1IP2:1;
unsigned int :1;
unsigned int DMA1IP8:1;
unsigned int DMA1IP9:1;
unsigned int DMA1IP2:1;
} IPC3bits;
#word IPC3bits = 0x0AA
#word IPC3 = 0x0AA

struct IPC4BITS {
unsigned int SI2C1IP0:1;
unsigned int SI2C1IP1:1;
unsigned int SI2C1IP2:1;
unsigned int :1;
unsigned int MI2C1IP4:1;
unsigned int MI2C1IP5:1;
unsigned int MI2C1IP2:1;
unsigned int :1;
unsigned int CMIP8:1;
unsigned int CMIP9:1;
unsigned int CMIP2:1;
unsigned int :1;
unsigned int CNIP12:1;
unsigned int CNIP13:1;
unsigned int CNIP2:1;
} IPC4bits;
#word IPC4bits = 0x0AC
#word IPC4 = 0x0AC

struct IPC5BITS {
unsigned int INT1IP0:1;
unsigned int INT1IP1:1;
unsigned int INT1IP2:1;
unsigned int :5;
unsigned int IC7IP8:1;
unsigned int IC7IP9:1;
unsigned int IC7IP2:1;
unsigned int :1;
unsigned int IC8IP12:1;
unsigned int IC8IP13:1;
unsigned int IC8IP2:1;
} IPC5bits;
#word IPC5bits = 0x0AE
#word IPC5 = 0x0AE

struct IPC6BITS {
unsigned int DMA2IP0:1;
unsigned int DMA2IP1:1;
unsigned int DMA2IP2:1;
unsigned int :1;
unsigned int OC3IP4:1;
unsigned int OC3IP5:1;
unsigned int OC3IP2:1;
unsigned int :1;
unsigned int OC4IP8:1;
unsigned int OC4IP9:1;
unsigned int OC4IP2:1;
unsigned int :1;
unsigned int T4IP12:1;
unsigned int T4IP13:1;
unsigned int T4IP2:1;
} IPC6bits;
#word IPC6bits = 0x0B0
#word IPC6 = 0x0B0

struct IPC7BITS {
unsigned int T5IP0:1;
unsigned int T5IP1:1;
unsigned int T5IP2:1;
unsigned int :1;
unsigned int INT2IP4:1;
unsigned int INT2IP5:1;
unsigned int INT2IP2:1;
unsigned int :1;
unsigned int U2RXIP8:1;
unsigned int U2RXIP9:1;
unsigned int U2RXIP2:1;
unsigned int :1;
unsigned int U2TXIP12:1;
unsigned int U2TXIP13:1;
unsigned int U2TXIP2:1;
} IPC7bits;
#word IPC7bits = 0x0B2
#word IPC7 = 0x0B2

struct IPC8BITS {
unsigned int SPI2EIP0:1;
unsigned int SPI2EIP1:1;
unsigned int SPI2EIP2:1;
unsigned int :1;
unsigned int SPI2IP4:1;
unsigned int SPI2IP5:1;
unsigned int SPI2IP2:1;
unsigned int :1;
unsigned int C1RXIP8:1;
unsigned int C1RXIP9:1;
unsigned int C1RXIP2:1;
unsigned int :1;
unsigned int C1IP12:1;
unsigned int C1IP13:1;
unsigned int C1IP2:1;
} IPC8bits;
#word IPC8bits = 0x0B4
#word IPC8 = 0x0B4

#word IPC9 = 0x0B6

struct IPC11BITS {
unsigned int :4;
unsigned int PMPIP4:1;
unsigned int PMPIP5:1;
unsigned int PMPIP2:1;
unsigned int :1;
unsigned int DMA4IP8:1;
unsigned int DMA4IP9:1;
unsigned int DMA4IP2:1;
} IPC11bits;
#word IPC11bits = 0x0BA
#word IPC11 = 0x0BA

struct IPC14BITS {
unsigned int :4;
unsigned int PWM1IP4:1;
unsigned int PWM1IP5:1;
unsigned int PWM1IP2:1;
unsigned int :1;
unsigned int QEI1IP8:1;
unsigned int QEI1IP9:1;
unsigned int QEI1IP2:1;
} IPC14bits;
#word IPC14bits = 0x0C0
#word IPC14 = 0x0C0

struct IPC15BITS {
unsigned int :4;
unsigned int DMA5IP4:1;
unsigned int DMA5IP5:1;
unsigned int DMA5IP2:1;
unsigned int :1;
unsigned int RTCIP8:1;
unsigned int RTCIP9:1;
unsigned int RTCIP2:1;
unsigned int :1;
unsigned int FLTA1IP12:1;
unsigned int FLTA1IP13:1;
unsigned int FLTA1IP2:1;
} IPC15bits;
#word IPC15bits = 0x0C2
#word IPC15 = 0x0C2

struct IPC16BITS {
unsigned int :4;
unsigned int U1EIP4:1;
unsigned int U1EIP5:1;
unsigned int U1EIP2:1;
unsigned int :1;
unsigned int U2EIP8:1;
unsigned int U2EIP9:1;
unsigned int U2EIP2:1;
unsigned int :1;
unsigned int CRCIP12:1;
unsigned int CRCIP13:1;
unsigned int CRCIP2:1;
} IPC16bits;
#word IPC16bits = 0x0C4
#word IPC16 = 0x0C4

struct IPC17BITS {
unsigned int DMA6IP0:1;
unsigned int DMA6IP1:1;
unsigned int DMA6IP2:1;
unsigned int :1;
unsigned int DMA7IP4:1;
unsigned int DMA7IP5:1;
unsigned int DMA7IP2:1;
unsigned int :1;
unsigned int C1TXIP8:1;
unsigned int C1TXIP9:1;
unsigned int C1TXIP2:1;
} IPC17bits;
#word IPC17bits = 0x0C6
#word IPC17 = 0x0C6

struct IPC18BITS {
unsigned int :4;
unsigned int PWM2IP4:1;
unsigned int PWM2IP5:1;
unsigned int PWM2IP2:1;
unsigned int :1;
unsigned int FLTA2IP8:1;
unsigned int FLTA2IP9:1;
unsigned int FLTA2IP2:1;
unsigned int :1;
unsigned int QEI2IP12:1;
unsigned int QEI2IP13:1;
unsigned int QEI2IP2:1;
} IPC18bits;
#word IPC18bits = 0x0C8
#word IPC18 = 0x0C8

struct IPC19BITS {
unsigned int :8;
unsigned int DAC1RIP8:1;
unsigned int DAC1RIP9:1;
unsigned int DAC1RIP2:1;
unsigned int :1;
unsigned int DAC1LIP12:1;
unsigned int DAC1LIP13:1;
unsigned int DAC1LIP2:1;
} IPC19bits;
#word IPC19bits = 0x0CA
#word IPC19 = 0x0CA

struct INTTREGBITS {
unsigned int VECNUM0:1;
unsigned int VECNUM1:1;
unsigned int VECNUM2:1;
unsigned int VECNUM3:1;
unsigned int VECNUM4:1;
unsigned int VECNUM5:1;
unsigned int VECNUM6:1;
unsigned int :1;
unsigned int ILR8:1;
unsigned int ILR9:1;
unsigned int ILR10:1;
unsigned int ILR3:1;
} INTTREGbits;
#word INTTREGbits = 0x0E0
#word INTTREG = 0x0E0

#word TMR1 = 0x100

#word PR1 = 0x102

struct T1CONBITS {
unsigned int :1;
unsigned int TCS:1;
unsigned int TSYNC:1;
unsigned int :1;
unsigned int TCKPS4:1;
unsigned int TCKPS5:1;
unsigned int TGATE:1;
unsigned int :6;
unsigned int TSIDL:1;
unsigned int :1;
unsigned int TON:1;
} T1CONbits;
#word T1CONbits = 0x104
#word T1CON = 0x104

#word TMR2 = 0x106

#word TMR3HLD = 0x108

#word TMR3 = 0x10A

#word PR2 = 0x10C

#word PR3 = 0x10E

struct T2CONBITS {
unsigned int :1;
unsigned int TCS:1;
unsigned int :1;
unsigned int T3:1;
unsigned int TCKPS4:1;
unsigned int TCKPS5:1;
unsigned int TGATE:1;
unsigned int :6;
unsigned int TSIDL:1;
unsigned int :1;
unsigned int TON:1;
} T2CONbits;
#word T2CONbits = 0x110
#word T2CON = 0x110

struct T3CONBITS {
unsigned int :1;
unsigned int TCS:1;
unsigned int :2;
unsigned int TCKPS4:1;
unsigned int TCKPS5:1;
unsigned int TGATE:1;
unsigned int :6;
unsigned int TSIDL:1;
unsigned int :1;
unsigned int TON:1;
} T3CONbits;
#word T3CONbits = 0x112
#word T3CON = 0x112

#word TMR4 = 0x114

#word TMR5HLD = 0x116

#word TMR5 = 0x118

#word PR4 = 0x11A

#word PR5 = 0x11C

struct T4CONBITS {
unsigned int :1;
unsigned int TCS:1;
unsigned int :1;
unsigned int T3:1;
unsigned int TCKPS4:1;
unsigned int TCKPS5:1;
unsigned int TGATE:1;
unsigned int :6;
unsigned int TSIDL:1;
unsigned int :1;
unsigned int TON:1;
} T4CONbits;
#word T4CONbits = 0x11E
#word T4CON = 0x11E

struct T5CONBITS {
unsigned int :1;
unsigned int TCS:1;
unsigned int :2;
unsigned int TCKPS4:1;
unsigned int TCKPS5:1;
unsigned int TGATE:1;
unsigned int :6;
unsigned int TSIDL:1;
unsigned int :1;
unsigned int TON:1;
} T5CONbits;
#word T5CONbits = 0x120
#word T5CON = 0x120

#word IC1BUF = 0x140

struct IC1CONBITS {
unsigned int ICM0:1;
unsigned int ICM1:1;
unsigned int ICM2:1;
unsigned int ICBNE:1;
unsigned int ICOV:1;
unsigned int ICI5:1;
unsigned int ICI6:1;
unsigned int ICTMR:1;
unsigned int :5;
unsigned int ICSIDL:1;
} IC1CONbits;
#word IC1CONbits = 0x142
#word IC1CON = 0x142

#word IC2BUF = 0x144

struct IC2CONBITS {
unsigned int ICM0:1;
unsigned int ICM1:1;
unsigned int ICM2:1;
unsigned int ICBNE:1;
unsigned int ICOV:1;
unsigned int ICI5:1;
unsigned int ICI6:1;
unsigned int ICTMR:1;
unsigned int :5;
unsigned int ICSIDL:1;
} IC2CONbits;
#word IC2CONbits = 0x146
#word IC2CON = 0x146

#word IC7BUF = 0x158

struct IC7CONBITS {
unsigned int ICM0:1;
unsigned int ICM1:1;
unsigned int ICM2:1;
unsigned int ICBNE:1;
unsigned int ICOV:1;
unsigned int ICI5:1;
unsigned int ICI6:1;
unsigned int ICTMR:1;
unsigned int :5;
unsigned int ICSIDL:1;
} IC7CONbits;
#word IC7CONbits = 0x15A
#word IC7CON = 0x15A

#word IC8BUF = 0x15C

struct IC8CONBITS {
unsigned int ICM0:1;
unsigned int ICM1:1;
unsigned int ICM2:1;
unsigned int ICBNE:1;
unsigned int ICOV:1;
unsigned int ICI5:1;
unsigned int ICI6:1;
unsigned int ICTMR:1;
unsigned int :5;
unsigned int ICSIDL:1;
} IC8CONbits;
#word IC8CONbits = 0x15E
#word IC8CON = 0x15E

#word OC1RS = 0x180

#word OC1R = 0x182

struct OC1CONBITS {
unsigned int OCM0:1;
unsigned int OCM1:1;
unsigned int OCM2:1;
unsigned int OCTSEL:1;
unsigned int OCFLT:1;
unsigned int :8;
unsigned int OCSIDL:1;
} OC1CONbits;
#word OC1CONbits = 0x184
#word OC1CON = 0x184

#word OC2RS = 0x186

#word OC2R = 0x188

struct OC2CONBITS {
unsigned int OCM0:1;
unsigned int OCM1:1;
unsigned int OCM2:1;
unsigned int OCTSEL:1;
unsigned int OCFLT:1;
unsigned int :8;
unsigned int OCSIDL:1;
} OC2CONbits;
#word OC2CONbits = 0x18A
#word OC2CON = 0x18A

#word OC3RS = 0x18C

#word OC3R = 0x18E

struct OC3CONBITS {
unsigned int OCM0:1;
unsigned int OCM1:1;
unsigned int OCM2:1;
unsigned int OCTSEL:1;
unsigned int OCFLT:1;
unsigned int :8;
unsigned int OCSIDL:1;
} OC3CONbits;
#word OC3CONbits = 0x190
#word OC3CON = 0x190

#word OC4RS = 0x192

#word OC4R = 0x194

struct OC4CONBITS {
unsigned int OCM0:1;
unsigned int OCM1:1;
unsigned int OCM2:1;
unsigned int OCTSEL:1;
unsigned int OCFLT:1;
unsigned int :8;
unsigned int OCSIDL:1;
} OC4CONbits;
#word OC4CONbits = 0x196
#word OC4CON = 0x196

struct P1TCONBITS {
unsigned int PTMOD0:1;
unsigned int PTMOD1:1;
unsigned int PTCKPS2:1;
unsigned int PTCKPS3:1;
unsigned int PTOPS4:1;
unsigned int PTOPS5:1;
unsigned int PTOPS6:1;
unsigned int PTOPS3:1;
unsigned int :5;
unsigned int PTSIDL:1;
unsigned int :1;
unsigned int PTEN:1;
} P1TCONbits;
#word P1TCONbits = 0x1C0
#word P1TCON = 0x1C0

struct P1TMRBITS {
unsigned int PTMR0:1;
unsigned int PTMR1:1;
unsigned int PTMR2:1;
unsigned int PTMR3:1;
unsigned int PTMR4:1;
unsigned int PTMR5:1;
unsigned int PTMR6:1;
unsigned int PTMR7:1;
unsigned int PTMR8:1;
unsigned int PTMR9:1;
unsigned int PTMR10:1;
unsigned int PTMR11:1;
unsigned int PTMR12:1;
unsigned int PTMR13:1;
unsigned int PTMR14:1;
unsigned int PTDIR:1;
} P1TMRbits;
#word P1TMRbits = 0x1C2
#word P1TMR = 0x1C2

#word P1TPER = 0x1C4

struct P1SECMPBITS {
unsigned int SEVTCMP0:1;
unsigned int SEVTCMP1:1;
unsigned int SEVTCMP2:1;
unsigned int SEVTCMP3:1;
unsigned int SEVTCMP4:1;
unsigned int SEVTCMP5:1;
unsigned int SEVTCMP6:1;
unsigned int SEVTCMP7:1;
unsigned int SEVTCMP8:1;
unsigned int SEVTCMP9:1;
unsigned int SEVTCMP10:1;
unsigned int SEVTCMP11:1;
unsigned int SEVTCMP12:1;
unsigned int SEVTCMP13:1;
unsigned int SEVTCMP14:1;
unsigned int SEVTDIR:1;
} P1SECMPbits;
#word P1SECMPbits = 0x1C6
#word P1SECMP = 0x1C6

struct PWM1CON1BITS {
unsigned int PEN1L:1;
unsigned int PEN2L:1;
unsigned int PEN3L:1;
unsigned int :1;
unsigned int PEN1H:1;
unsigned int PEN2H:1;
unsigned int PEN3H:1;
unsigned int :1;
unsigned int PMOD1:1;
unsigned int PMOD2:1;
unsigned int PMOD3:1;
} PWM1CON1bits;
#word PWM1CON1bits = 0x01C8
#word PWM1CON1 = 0x01C8
struct P1DTCON1BITS {
union {
struct {
unsigned DTA:6;
unsigned DTAPS:2;
unsigned DTB:6;
unsigned DTBPS:2;
};
struct {
unsigned DTA0:1;
unsigned DTA1:1;
unsigned DTA2:1;
unsigned DTA3:1;
unsigned DTA4:1;
unsigned DTA5:1;
unsigned DTAPS0:1;
unsigned DTAPS1:1;
unsigned DTB0:1;
unsigned DTB1:1;
unsigned DTB2:1;
unsigned DTB3:1;
unsigned DTB4:1;
unsigned DTB5:1;
unsigned DTBPS0:1;
unsigned DTBPS1:1;
};
};
} P1DTCON1bits;
#word P1DTCON1bits = 0x01CC
#word P1DTCON1 = 0x01CC
//~~~~~~~~~~~~~~~~~~~
//typedef struct PWMCON1BITS {
// unsigned int PEN1L:1;
// unsigned int PEN2L:1;
// unsigned int PEN3L:1;
// unsigned int :1;
// unsigned int PEN1H:1;
// unsigned int PEN2H:1;
// unsigned int PEN3H:1;
// unsigned int :1;
// unsigned int PMOD1:1;
// unsigned int PMOD2:1;
// unsigned int PMOD3:1;
//} PWMCON1bits;


struct P1FLTACONBITS {
unsigned int FAEN1:1;
unsigned int FAEN2:1;
unsigned int FAEN3:1;
unsigned int :4;
unsigned int FLTAM:1;
unsigned int FAOV1L:1;
unsigned int FAOV1H:1;
unsigned int FAOV2L:1;
unsigned int FAOV2H:1;
unsigned int FAOV3L:1;
unsigned int FAOV3H:1;
} P1FLTACONbits;
#word P1FLTACONbits = 0x01D0
#word P1FLTACON = 0x01D0

///////
struct P1OVDCONBITS {
unsigned int POUT1L:1;
unsigned int POUT1H:1;
unsigned int POUT2L:1;
unsigned int POUT2H:1;
unsigned int POUT3L:1;
unsigned int POUT3H:1;
unsigned int :2;
unsigned int POVD1L:1;
unsigned int POVD1H:1;
unsigned int POVD2L:1;
unsigned int POVD2H:1;
unsigned int POVD3L:1;
unsigned int POVD3H:1;

} P1OVDCONbits;
#word P1OVDCONbits = 0x01D4
#word P1OVDCON = 0x01D4
//~~~~~~~~~~~~~~~~~~~

struct PWM1CON2BITS {
// unsigned int UDIS:1;
// unsigned int OSYNC:1;
// unsigned int IUE:1;
// unsigned int :5;
// unsigned int SEVOPS8:1;
// unsigned int SEVOPS9:1;
// unsigned int SEVOPS10:1;
// unsigned int SEVOPS3:1;
union {
struct {
unsigned int UDIS:1;
unsigned int OSYNC:1;
unsigned int IUE:1;
unsigned int :5;
unsigned int SEVOPS:4;
};
struct {
unsigned int :8;
unsigned int SEVOPS0:1;
unsigned int SEVOPS1:1;
unsigned int SEVOPS2:1;
unsigned int SEVOPS3:1;
};
};
} PWM1CON2bits;
#word PWM1CON2bits = 0x1CA
#word PWM1CON2 = 0x1CA

struct DTCON1BITS {
unsigned int DTA0:1;
unsigned int DTA1:1;
unsigned int DTA2:1;
unsigned int DTA3:1;
unsigned int DTA4:1;
unsigned int DTA5:1;
unsigned int DTAPS6:1;
unsigned int DTAPS7:1;
unsigned int DTB8:1;
unsigned int DTB9:1;
unsigned int DTB10:1;
unsigned int DTB11:1;
unsigned int DTB12:1;
unsigned int DTB13:1;
unsigned int DTBPS14:1;
unsigned int DTBPS1:1;
} DTCON1bits;
#word DTCON1bits = 0x1CC
#word DTCON1 = 0x1CC

struct DTCON2BITS {
unsigned int DTS1I:1;
unsigned int DTS1A:1;
unsigned int DTS2I:1;
unsigned int DTS2A:1;
unsigned int DTS3I:1;
unsigned int DTS3A:1;
} DTCON2bits;
#word DTCON2bits = 0x1CE
#word DTCON2 = 0x1CE

struct FLTACONBITS {
unsigned int FAEN0:1;
unsigned int FAEN1:1;
unsigned int FAEN3:1;
unsigned int :4;
unsigned int FLTAM:1;
unsigned int FAOV1L:1;
unsigned int FAOV1H:1;
unsigned int FAOV2L:1;
unsigned int FAOV2H:1;
unsigned int FAOV3L:1;
unsigned int FAOV3H:1;
} FLTACONbits;
#word FLTACONbits = 0x1D0
#word FLTACON = 0x1D0

struct OVDCONBITS {
unsigned int POUT1L:1;
unsigned int P
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