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A Special question about "FPGA and 16F877"
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Ttelmah



Joined: 11 Mar 2010
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PostPosted: Fri Aug 21, 2020 12:58 am     Reply with quote

In this case it turned out to be a dry joint in the input side of the switch
mode PSU. The hardest thing is opening the sets in many cases....
temtronic



Joined: 01 Jul 2010
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PostPosted: Fri Aug 21, 2020 6:25 am     Reply with quote

yeah, you have to destroy one identical unit to hopefully see how it was assembled.... life was simpler long ago when these things called screws held cases on....
'they' are trying hard to make us a totally disposable society.. and that ain't right !!!
hmm, anyone need a tube of PIC16C84 ??
newguy



Joined: 24 Jun 2004
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PostPosted: Fri Aug 21, 2020 9:22 am     Reply with quote

I agree with the disposable sentiment but I do like how small/integrated things have become. ...Can you imagine mounting a 26" console television on a wall? Wink
Ttelmah



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PostPosted: Fri Aug 21, 2020 12:41 pm     Reply with quote

However the size difference there is just the technology shift from using a CRT,
to using plasma or LCD. The case changes don't make that much difference.
I have a 55" set, that is only 1.25" deep, yet still has screws to remove the
case.
newguy



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PostPosted: Fri Aug 21, 2020 3:43 pm     Reply with quote

I've not had my hands on a lot of flat screen TVs, but they all have had screws holding them together. Matter of fact...

I have a relatively new LG TV. The online streaming services (netflix, amazon) never really worked well because the TV had *major* issues connecting to my home wi-fi network. Tried everything, including using a power line LAN module to try a hard wired approach instead. Nothing really helped. When the wi-fi connection would act up, the only thing that would fix it (temporarily) would be to flip the breaker (too difficult to get behind the TV to yank its power cord). This past winter I finally had enough one evening. Googled my model and "wifi problems" and found a post by some guy who, in desperation, took the TV apart and, in the spirit of it-can't-hurt, straightened the flexible PCB connecting the wi-fi module with main board. Which corrected his issues. ...So, at about 9:30pm on a Saturday evening, so did I. And it worked a treat!
temtronic



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PostPosted: Fri Aug 21, 2020 4:41 pm     Reply with quote

wanna have REAL 'fun' ? tear apart the remote control for my TV cable box !
NO screws....'magical' plastic clips, LOTS of them...grrrr...
On my 'todo list', use a PIC to mimic the control and use a GOOD keypad...
then again there's nothing good on TV so.... maye I'll go back to the ebrake trailer project or ...

sigh
Jay
ressas



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PostPosted: Sat Aug 22, 2020 1:33 am     Reply with quote

Can we do transistor level operations while programming the FPGA? Or are we programming at a higher level
Ttelmah



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PostPosted: Sat Aug 22, 2020 1:39 am     Reply with quote

Generally gate level, not individual transistors. However some have output
drive devices that can be individually assigned. Depends on the device, what
software is being used. etc. etc....
bkamen



Joined: 07 Jan 2004
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PostPosted: Sun Oct 04, 2020 12:09 am     Reply with quote

Right.

One doesn't control the transistors.

With Xilinx, they're called primitives.

For example:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/spartan6_hdl.pdf

An FPGA isn't just about gates either. Modern day FPGAs have all sorts of pre-made goodies for the designer to use.

You don't have to build a RAM block, blocks of ram already exist on the die. There are usually wizards to control how they're configured into FIFOs of whatever you need or RAM for scratch pads and so on.

There are PLLs. There are high-speed serial-to-parallel and parallel-to-serial shifters right near some of the I/O pads to build high speed de/serializers for things like LVDS buses.

I've been working the the Xilinx Zynq-020 now for years with one client. Those have 32bit ARM CPUs built on the die and run Linux. So in cases where we need special peripherals to interface to a CPU, I just design them. (high speed particle counters or specialized CMOS imagers)

It's tons of fun. And a lot of headaches sometimes.

Once you start writing for FPGAs, you realize how probably all of Microchip's PIC families are written in Verilog or (more likely) VHDL because they spew out MCUs within the same family like popcorn.

VHDL and Verilog are not limited to designing only FPGA...

It's neat stuff.
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Ttelmah



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PostPosted: Sun Oct 04, 2020 12:35 am     Reply with quote

Yes, except that they produce different bugs from the same peripheral on
different chips.... They are using die level designer, not an FPGA, and this
has it's own optimiser that introduces problems.... :(
bkamen



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PostPosted: Sun Oct 04, 2020 9:33 am     Reply with quote

Ttelmah wrote:
Yes, except that they produce different bugs from the same peripheral on
different chips.... They are using die level designer, not an FPGA, and this
has it's own optimiser that introduces problems.... :(


Yep. Exactly.

The Verilog/VHDL "compilers" can be really tricky/picky.

I've seen some really horrid compilers in my time that complain about text book examples of properly written code only to have the same compiler be fine with tech support recommended blocks of code that are explicitly considered verboten.

And then you get into what/how the components are defined in the die Fab's library. Oy.

I just wanted to point out that HDLs had uses other than just FPGAs.

p.s. The other funny thing about FPGAs is propagation time matters. When designing an FPGA, constraints describing critical timing paths have to be written so the compiler can make sure paths are optimized for signals. It sucks when you have a databus and one of the data lines from the outside world always seems to be a few nanoseconds late and a dollar short. Razz Razz
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Ttelmah



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PostPosted: Sun Oct 04, 2020 11:28 am     Reply with quote

Absolutely. The problems are also made worse when board capacitances
and different switching thresholds slightly shift timings between the
external signals.... Sad
(Whimper mode).
bkamen



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PostPosted: Tue Oct 13, 2020 1:01 am     Reply with quote

Yep.

I sure don't remember the last time I had to write a constraints file to deal with setup/hold timings for a PIC MCU.

LoL....
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