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kWoody_uk
Joined: 29 Jan 2015
Posts: 51
Location: United Kingdom
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| Pic18f57q43 CLC module independence |
 Posted: Sun Nov 09, 2025 5:24 am |
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Hi guys.
There are eight clc modules on this chip. Are they all truly independent from each other (or rather, can they be)?
Reason I ask is that I've configured 3 in a certain way so that they're connected, then I've done the same with another 3. The required config works ok for the first 3, but they are affecting the output of the other three. I've checked the PPS setup and apparently it's correct.
I'm on compiler 5.105.
Any input would be welcome thanks |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19982
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| Posted: Sun Nov 09, 2025 6:47 am |
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Er.
Read the first paragraph of section 22 in the sheet.
There are up to 256 inputs, _routed down to just four internal lines_, that
can then be nouted to eight CLC modules to up to eight outputs.
The problem is if you need more than the four lines.
So long as logic only needs the four source lines, you can do what you
want, but if your logic needs more than the four lines, you have a problem. |
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kWoody_uk
Joined: 29 Jan 2015
Posts: 51
Location: United Kingdom
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| Posted: Sun Nov 09, 2025 6:54 am |
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That reads differently to what I'm looking at...
| Quote: | | The logic cell takes up to 256 input signals and, through the use of configurable gates, reduces those inputs to four logic lines that drive one of eight selectable single-output logic functions. |
Yours makes it sound like the four inputs are common to all eight clc modules |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19982
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| Posted: Sun Nov 09, 2025 8:14 am |
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Yes, I'm not sure. However the interesting part is figure 22-2, where it shows
the source routes into the gates as stretching upwards and downwards as
if they extend to the other gates. This is the behaviour that seems to occur
when you try to use more inputs on several gates.....  |
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kWoody_uk
Joined: 29 Jan 2015
Posts: 51
Location: United Kingdom
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| Posted: Sun Nov 09, 2025 8:21 am |
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| I know EXACTLY what you mean. I thought the same when I was trying to get my head around it: it's a bit vague. Guess I'll do a bit more experimentation to check things out and I'll report back. 👍🏼 |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19982
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| Posted: Mon Nov 10, 2025 10:41 am |
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The problem is that Microchip don't seem to be documenting how the
interconnections actually work at all well.
[url]
https://www.microcontrollertips.com/microchip-pic-microcontroller-configurable-logic-cells-clc/
[/url]
Whether they are independent or not seems to be very poorly documented,
and changes from chip to chip.
The reference to DS41631B is what I had seen before with the limit at
4 sources, but this is not true for several of the chips. |
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temtronic
Joined: 01 Jul 2010
Posts: 9594
Location: Greensville,Ontario
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| Posted: Mon Nov 10, 2025 1:07 pm |
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I briefly looked into the CLC stuff, thinking I could use it to replace an 'ancient' PLA used in a HD interface to a Z-80.
Whatever I read seemed to say only 4 'sections' or whatever is the correct term, naturally I needed 8.
I didn't go any further but surely MC has more documentation on them ?? |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19982
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| Posted: Mon Nov 10, 2025 10:29 pm |
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I was on the same trail a little while ago, and found that I could not have
more than 4 actual source signals in use. This was a slightly older chip
though than the poster is using. Historically Microchip documentation was
great, bit on many recent peripherals it has degenerated into 'poor'.
It'd be dead simple for them to just say how many input lines can be
used at once on each chip. Unfortunately this does not seem to be being
done. That the poster is having the behaviour he is seeing, suggests there
is a limit on this chip. |
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drh
Joined: 12 Jul 2004
Posts: 194
Location: Hemet, California USA
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| Posted: Tue Nov 11, 2025 5:33 pm |
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You should be able to get more information on the Microchip user forum.
_________________
David |
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kWoody_uk
Joined: 29 Jan 2015
Posts: 51
Location: United Kingdom
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| Posted: Wed Nov 12, 2025 8:00 am |
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Thanks for the input guys.
So, I have managed to get the following working on real hardware:-
| Code: |
/*
CLC setup equivalent configuration (there are two of these being defined):-
_______
-------------------------------------------| |
| _______ | |
On/Offx ----*----NOT----| | | & |------ FETBypassEnableSetx
| | _______ | |
| & |-------| S Q |------|_______|
/FFx -------*-----------| | | |
| |_______| | LATCH |
| | |
-----NOT--------------------|_R_____|
Operation:-
On/Off is a manual software control for enabling the FETBypass.
/FF is the overcurrent flag (high = no fault, low = fault).
When /FF is high, setting On/Off high enables the FETBypass.
If /FF goes low, the latch resets and disables the FETBypass.
It stays off until On/Off is taken low and /FF returns high.
This latching action prevents automatic re-enable after a fault.
*/
// Channel A setup
// This is the First AND gate setup
clc1_setup_input(1, CLC_BYPASS_FET_ONOFFA); // This is software control which is actually manual ONOFFA for logic control
clc1_setup_input(2, CLC_BYPASS_FET_FFA); // FaultFlagAInPin
clc1_setup_gate(1, CLC_GATE_INVERTED_INPUT_1); // This is the first input to the AND gate
clc1_setup_gate(2, CLC_GATE_NON_INVERTED_INPUT_2); // This is the second input to the AND gate
clc1_setup_gate(3, CLC_GATE_SET); // This is the third input to the AND gate (unused but set high)
clc1_setup_gate(4, CLC_GATE_SET); // This is the forth input to the AND gate (unused but set high)
setup_clc1( CLC_ENABLED | CLC_MODE_AND );
// This is the FlipFlop Latch setup
clc2_setup_input(1, CLC_INPUT_CLC1); // Output from clc1
clc2_setup_input(3, CLC_BYPASS_FET_FFA);
clc2_setup_gate(1, CLC_GATE_NON_INVERTED_INPUT_1); // This is the first input to S of latch
clc2_setup_gate(2, CLC_GATE_CLEAR); // This is the second input to S of latch (not used)
clc2_setup_gate(3, CLC_GATE_INVERTED_INPUT_3); // This is the first input to R of latch
clc2_setup_gate(4, CLC_GATE_CLEAR); // This is the second input to R of latch (not used)
setup_clc2( CLC_ENABLED | CLC_MODE_SR_LATCH );
// This is the final AND gate setup
clc7_setup_input(1, CLC_INPUT_CLC2); // Output from clc2
clc7_setup_input(2, CLC_BYPASS_FET_ONOFFA); // This is software control which is actually manual ONOFFA for logic control
clc7_setup_gate(1, CLC_GATE_NON_INVERTED_INPUT_1); // This is the first input to the AND gate
clc7_setup_gate(2, CLC_GATE_NON_INVERTED_INPUT_2); // This is the second input to the AND gate
clc7_setup_gate(3, CLC_GATE_SET); // This is the third input to the AND gate (unused but set high)
clc7_setup_gate(4, CLC_GATE_SET); // This is the forth input to the AND gate (unused but set high)
setup_clc7( CLC_ENABLED | CLC_MODE_AND );
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This is then repeated with clc's 4, 5 and 8.
The problem I was having relating to the first set affecting the second, was that after ccs clc functions disabled the output of the CLC_BYPASS_FET_ONOFFA input to the CLC, this pin is extremely susceptible to any noise/crosstalk, and as they are not connected to any external hardware (pullups/downs), they were being influenced negatively.
To sort this out, I set both IO pins to output_low right after these setups, which sorted things out. |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19982
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| Posted: Wed Nov 12, 2025 8:43 am |
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OK. So this chip does have them independent. Great to know. 
The FET makes sense. An input like this is very high impedance and
only needs a small voltage to trigger.
Well done. |
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