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the bootloader looks ok but the code doesn't run
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ciccioc74



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the bootloader looks ok but the code doesn't run
PostPosted: Tue Sep 01, 2020 7:41 am     Reply with quote

hi i have a board with pic18f45k50 (led on C0 and C2, button on RE3 crystal 8MHz clock 32MHz USB ). The board is ok, the led blinks. Now i wish to use a bootloader by USB HID. I try MLA bootloader PIC18 Non-J C18 (the flasher is USB HID v2.90a). When i plug the board (without button pressed) the flasher recognizes the board, the led blinks. I use the flasher but my application doesn't run.
The bootloader is from 0x00 to 0xFFF.

I use CCS C compiler rev 5.015 on MPLAB X IDE.

In the firmware i insert:
Code:
#define LOADER_SIZE                 (0xFFF)
#define LOADER_START                (0)
#define LOADER_END                  (LOADER_SIZE)
#define APPLICATION_START           (LOADER_SIZE+1)
#define APPLICATION_END             (getenv("PROGRAM_MEMORY")-1)
#define APPLICATION_ISR             (APPLICATION_START+8)

#ifndef _bootloader
 //in the application, this moves the reset and isr vector out of the bootload
 //space.  it then reserves the loader space from being used by the application.
 #BUILD(RESET=APPLICATION_START, INTERRUPT=APPLICATION_ISR)
 #org 0, LOADER_END {}
#endif


Where am i wrong?
ciccioc74



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PostPosted: Tue Sep 01, 2020 10:12 am     Reply with quote

i think the problem should be in the fuses
in my firmware is:
Code:


#FUSES MCLR
#FUSES NOWDT                    //No Watch Dog Timer
#FUSES WDT128                   //Watch Dog Timer uses 1:128 Postscale
#FUSES NOBROWNOUT               //No brownout reset
#FUSES NOLVP                    //No low voltage prgming, B3(PIC16) or B5(PIC18) used for I/O
#FUSES NOXINST                  //Extended set extension and Indexed Addressing mode disabled (Legacy mode)
#FUSES ICSP1
#FUSES NOPROTECT                //Code not protected from reading
//#FUSES CPB
//#FUSES CPD
#FUSES BROWNOUT               //No brownout reset
#FUSES BORV22                   //Brownout reset at 2.0V
#FUSES CCP2C1                   //ccp pwm su c1
#FUSES PLLEN
#FUSES PLL4X
#FUSES NOCPUDIV
#FUSES HSH

#use delay(clock=32000000,crystal=8000000)


In the bootloader is:
Code:

 #pragma config PLLSEL   = PLL3X     // PLL Selection (3x clock multiplier)
    #pragma config CFGPLLEN = OFF       // PLL Enable Configuration bit (PLL Disabled (firmware controlled))
    #pragma config CPUDIV   = NOCLKDIV  // CPU System Clock Postscaler (CPU uses system clock (no divide))
    #pragma config LS48MHZ  = SYS48X8   // Low Speed USB mode with 48 MHz system clock (System clock at 48 MHz, USB clock divider is set to 8)
    #pragma config FOSC     = INTOSCIO  // Oscillator Selection (Internal oscillator)
    #pragma config PCLKEN   = OFF       // Primary Oscillator Shutdown (Primary oscillator shutdown firmware controlled)
    #pragma config FCMEN    = OFF       // Fail-Safe Clock Monitor (Fail-Safe Clock Monitor disabled)
    #pragma config IESO     = OFF       // Internal/External Oscillator Switchover (Oscillator Switchover mode disabled)
    #pragma config nPWRTEN  = OFF       // Power-up Timer Enable (Power up timer disabled)
    #pragma config BOREN    = SBORDIS   // Brown-out Reset Enable (BOR enabled in hardware (SBOREN is ignored))
    #pragma config BORV     = 190      // Brown-out Reset Voltage (BOR set to 1.9V nominal)
    #pragma config nLPBOR   = ON        // Low-Power Brown-out Reset (Low-Power Brown-out Reset enabled)
    #pragma config WDTEN    = SWON      // Watchdog Timer Enable bits (WDT controlled by firmware (SWDTEN enabled))
    #pragma config WDTPS    = 32768     // Watchdog Timer Postscaler (1:32768)
    #pragma config CCP2MX   = RC1       // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
    #pragma config PBADEN   = OFF       // PORTB A/D Enable bit (PORTB<5:0> pins are configured as digital I/O on Reset)
    #pragma config T3CMX    = RC0       // Timer3 Clock Input MUX bit (T3CKI function is on RC0)
    #pragma config SDOMX    = RC7       // SDO Output MUX bit (SDO function is on RC7)
    #pragma config MCLRE    = ON        // Master Clear Reset Pin Enable (MCLR pin enabled; RE3 input disabled)
    #pragma config STVREN   = ON        // Stack Full/Underflow Reset (Stack full/underflow will cause Reset)
    #pragma config LVP      = OFF       // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
    #pragma config ICPRT    = OFF       // Dedicated In-Circuit Debug/Programming Port Enable (ICPORT disabled)
    #pragma config XINST    = OFF       // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled)
    #pragma config CP0      = OFF       // Block 0 Code Protect (Block 0 is not code-protected)
    #pragma config CP1      = OFF       // Block 1 Code Protect (Block 1 is not code-protected)
    #pragma config CP2      = OFF       // Block 2 Code Protect (Block 2 is not code-protected)
    #pragma config CP3      = OFF       // Block 3 Code Protect (Block 3 is not code-protected)
    #pragma config CPB      = OFF       // Boot Block Code Protect (Boot block is not code-protected)
    #pragma config CPD      = OFF       // Data EEPROM Code Protect (Data EEPROM is not code-protected)
    #pragma config WRT0     = OFF       // Block 0 Write Protect (Block 0 (0800-1FFFh) is not write-protected)
    #pragma config WRT1     = OFF       // Block 1 Write Protect (Block 1 (2000-3FFFh) is not write-protected)
    #pragma config WRT2     = OFF       // Block 2 Write Protect (Block 2 (04000-5FFFh) is not write-protected)
    #pragma config WRT3     = OFF       // Block 3 Write Protect (Block 3 (06000-7FFFh) is not write-protected)
    #pragma config WRTC     = OFF       // Configuration Registers Write Protect (Configuration registers (300000-3000FFh) are not write-protected)
    #pragma config WRTB     = OFF       // Boot Block Write Protect (Boot block (0000-7FFh) is not write-protected)
    #pragma config WRTD     = OFF       // Data EEPROM Write Protect (Data EEPROM is not write-protected)
    #pragma config EBTR0    = OFF       // Block 0 Table Read Protect (Block 0 is not protected from table reads executed in other blocks)
    #pragma config EBTR1    = OFF       // Block 1 Table Read Protect (Block 1 is not protected from table reads executed in other blocks)
    #pragma config EBTR2    = OFF       // Block 2 Table Read Protect (Block 2 is not protected from table reads executed in other blocks)
    #pragma config EBTR3    = OFF       // Block 3 Table Read Protect (Block 3 is not protected from table reads executed in other blocks)
    #pragma config EBTRB    = OFF       // Boot Block Table Read Protect (Boot block is not protected from table reads executed in other blocks)
temtronic



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PostPosted: Tue Sep 01, 2020 10:50 am     Reply with quote

I don't use that PIC or bootloader but from past posts, the fuses for BOTH your program and bootloader should be the same..
hopefully someone using your PIC/bootloader will reply soon.....
Ttelmah



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PostPosted: Tue Sep 01, 2020 11:19 am     Reply with quote

Yes. The correct setting for the application is always:

#FUSES NONE

The bootloader fuses have to be correct for the final application. The
bootloader cannot change the programmed fuses.
jeremiah



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PostPosted: Tue Sep 01, 2020 8:41 pm     Reply with quote

In addition, you only want
Code:

#use delay(clock=32000000)


As adding the other parameter can generate fuses. So combination of:

Code:

#fuses NONE
#use delay(clock=32000000)


After that, if you still have problems, try using your programmer to read the hex off the chip after you program it and see if the hex matches what you expect.
ciccioc74



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PostPosted: Wed Sep 02, 2020 7:28 am     Reply with quote

Thank you very much for your kind replies.
I did the tests you say.
I copied the fuses settings from the c18 bootloader to CCS and the led blinks (the configuration is ok). Then I used the bootloader settings but the program doesn't work.
This is my fw:
Code:
#include <18F45K50.h>


//how big is the bootloader?
//the bootloader will reside from address 0x0000 to this location.  the
//application will then sit at this location+1 to the end of program memory.
#define LOADER_SIZE                 (0xFFF)
#define LOADER_START                (0)
#define LOADER_END                  (LOADER_SIZE)
#define APPLICATION_START           (LOADER_SIZE+1)
#define APPLICATION_END             (getenv("PROGRAM_MEMORY")-1)
#define APPLICATION_ISR             (APPLICATION_START+8)

#define _bootloader

#ifndef _bootloader
    //in the application, this moves the reset and isr vector out of the bootload
    //space.  it then reserves the loader space from being used by the application.
    #BUILD(RESET=APPLICATION_START, INTERRUPT=APPLICATION_ISR)
    #org 0, LOADER_END {}


   #fuses NONE
   #use delay(clock=32000000)

#else
   
     
    #FUSES NOPLLEN
    #FUSES PLL3X
    #FUSES NOCPUDIV
    #FUSES LS48MHZ
    #FUSES INTRC_IO//HSH
    #FUSES PRIMARY_SW
    #FUSES NOFCMEN
    #FUSES NOIESO
    #FUSES NOPUT
    #FUSES BROWNOUT               //No brownout reset
    #FUSES BORV25                   //Brownout reset at 1.9V
    #FUSES LPBOR
    #FUSES WDT_SW
    #FUSES WDT32768
    #FUSES CCP2C1                   //ccp pwm su c1
    #FUSES NOPBADEN
    #FUSES T3CKC0
    #FUSES SDOC7//cambiare con SDOB3
    #FUSES NOMCLR
    #FUSES STVREN
    #FUSES NOLVP                    //No low voltage prgming, B3(PIC16) or B5(PIC18) used for I/O
    #FUSES ICSP2
    #FUSES NOXINST                  //Extended set extension and Indexed Addressing mode disabled (Legacy mode)   
    #FUSES NOPROTECT                //Code not protected from reading
    #FUSES NOCPB
    #FUSES NOCPD

    #use delay(clock=32000000)

#endif


 /* This is C18 Bootloader fuses
 * #pragma config PLLSEL   = PLL3X     // PLL Selection (3x clock multiplier)
    #pragma config CFGPLLEN = OFF       // PLL Enable Configuration bit (PLL Disabled (firmware controlled))
    #pragma config CPUDIV   = NOCLKDIV  // CPU System Clock Postscaler (CPU uses system clock (no divide))
    #pragma config LS48MHZ  = SYS48X8   // Low Speed USB mode with 48 MHz system clock (System clock at 48 MHz, USB clock divider is set to 8)
    #pragma config FOSC     = INTOSCIO  // Oscillator Selection (Internal oscillator)
    #pragma config PCLKEN   = OFF       // Primary Oscillator Shutdown (Primary oscillator shutdown firmware controlled)
    #pragma config FCMEN    = OFF       // Fail-Safe Clock Monitor (Fail-Safe Clock Monitor disabled)
    #pragma config IESO     = OFF       // Internal/External Oscillator Switchover (Oscillator Switchover mode disabled)
    #pragma config nPWRTEN  = OFF       // Power-up Timer Enable (Power up timer disabled)
    #pragma config BOREN    = SBORDIS   // Brown-out Reset Enable (BOR enabled in hardware (SBOREN is ignored))
    #pragma config BORV     = 190      // Brown-out Reset Voltage (BOR set to 1.9V nominal)
    #pragma config nLPBOR   = ON        // Low-Power Brown-out Reset (Low-Power Brown-out Reset enabled)
    #pragma config WDTEN    = SWON      // Watchdog Timer Enable bits (WDT controlled by firmware (SWDTEN enabled))
    #pragma config WDTPS    = 32768     // Watchdog Timer Postscaler (1:32768)
    #pragma config CCP2MX   = RC1       // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
    #pragma config PBADEN   = OFF       // PORTB A/D Enable bit (PORTB<5:0> pins are configured as digital I/O on Reset)
    #pragma config T3CMX    = RC0       // Timer3 Clock Input MUX bit (T3CKI function is on RC0)
    #pragma config SDOMX    = RC7       // SDO Output MUX bit (SDO function is on RC7)
    #pragma config MCLRE    = OFF        // Master Clear Reset Pin Enable (MCLR pin enabled; RE3 input disabled)
    #pragma config STVREN   = ON        // Stack Full/Underflow Reset (Stack full/underflow will cause Reset)
    #pragma config LVP      = OFF       // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
    #pragma config ICPRT    = OFF       // Dedicated In-Circuit Debug/Programming Port Enable (ICPORT disabled)
    #pragma config XINST    = OFF       // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled)
    #pragma config CP0      = OFF       // Block 0 Code Protect (Block 0 is not code-protected)
    #pragma config CP1      = OFF       // Block 1 Code Protect (Block 1 is not code-protected)
    #pragma config CP2      = OFF       // Block 2 Code Protect (Block 2 is not code-protected)
    #pragma config CP3      = OFF       // Block 3 Code Protect (Block 3 is not code-protected)
    #pragma config CPB      = OFF       // Boot Block Code Protect (Boot block is not code-protected)
    #pragma config CPD      = OFF       // Data EEPROM Code Protect (Data EEPROM is not code-protected)
    #pragma config WRT0     = OFF       // Block 0 Write Protect (Block 0 (0800-1FFFh) is not write-protected)
    #pragma config WRT1     = OFF       // Block 1 Write Protect (Block 1 (2000-3FFFh) is not write-protected)
    #pragma config WRT2     = OFF       // Block 2 Write Protect (Block 2 (04000-5FFFh) is not write-protected)
    #pragma config WRT3     = OFF       // Block 3 Write Protect (Block 3 (06000-7FFFh) is not write-protected)
    #pragma config WRTC     = OFF       // Configuration Registers Write Protect (Configuration registers (300000-3000FFh) are not write-protected)
    #pragma config WRTB     = OFF       // Boot Block Write Protect (Boot block (0000-7FFh) is not write-protected)
    #pragma config WRTD     = OFF       // Data EEPROM Write Protect (Data EEPROM is not write-protected)
    #pragma config EBTR0    = OFF       // Block 0 Table Read Protect (Block 0 is not protected from table reads executed in other blocks)
    #pragma config EBTR1    = OFF       // Block 1 Table Read Protect (Block 1 is not protected from table reads executed in other blocks)
    #pragma config EBTR2    = OFF       // Block 2 Table Read Protect (Block 2 is not protected from table reads executed in other blocks)
    #pragma config EBTR3    = OFF       // Block 3 Table Read Protect (Block 3 is not protected from table reads executed in other blocks)
    #pragma config EBTRB    = OFF       // Boot Block Table Read Protect (Boot block is not protected from table reads executed in other blocks)

*/

#include <stdio.h>
#include <stdlib.h>

#define sw1   PIN_E3
#define LED3   PIN_C0
#define LED4   PIN_C2

void main() {
     
    disable_interrupts (GLOBAL) ;
    OUTPUT_A(0);
    set_tris_a (0b00101011);
    OUTPUT_B(0);
    set_tris_b (0b01111100);
    OUTPUT_C(0);
    set_tris_c (0b10000000);
    OUTPUT_D(0);
    set_tris_d (0);
    OUTPUT_E(0);
    set_tris_e (0b1011);
 
     while (1) {
         output_toggle (LED4) ;
         delay_ms(500);
     }
}


The fuses settings is: 0X0821, 0X3E1F, 0X1100, 0X0081 then all to "1".
Ttelmah



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PostPosted: Wed Sep 02, 2020 7:59 am     Reply with quote

The program actually 'running', is dependant of the bootloader code
correctly deciding you don't want to bootload, and jumping to
the actual application. In the examples. this is:
Code:

//This tells the loader where the application should be
#org LOADER_END+1,LOADER_END+3
void application(void) {
  while(TRUE);
}

void main(void) {

   if(!input(PUSH_BUTTON))
   {
      printf("\r\nBootloader Version 1.0\r\n");
   
      // Let the user know it is ready to accept a download
      printf("\r\nWaiting for download...");
      load_program();
   }
   application(); //This is what actually executes the application....
}


Your size is wrong. The USB bootloader for a PCH chip (PIC18), is
0x2000 long, not 0x1000........

Look at usb_bootloader.h
Quote:

#if defined(__PCM__)
#define LOADER_SIZE (0x1000)
#elif defined(__PCH__)
#define LOADER_SIZE (0x2000) //note this......
#elif defined(__PCD__)
#define LOADER_SIZE (0x2000)
#else
#error not supported
#endif
ciccioc74



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PostPosted: Wed Sep 02, 2020 8:22 am     Reply with quote

Quote:

The program actually 'running', is dependant of the bootloader code

yes i now. I meant "the led don't blinks"

Quote:
Your size is wrong. The USB bootloader for a PCH chip (PIC18), is
0x2000 long, not 0x1000........


?? i don't understand. In bootloader source i read:

Code:

//Constants
#define REMAPPED_APPLICATION_RESET_VECTOR       0x1000
#define REMAPPED_APPLICATION_HIGH_ISR_VECTOR    0x1008
#define REMAPPED_APPLICATION_LOW_ISR_VECTOR     0x1018
#define BOOTLOADER_ABSOLUTE_ENTRY_ADDRESS       0x001C  //Execute a "_asm goto 0x001C _endasm" instruction, if you want to enter the bootloader mode from the application via software


and with Pickit2 i read the bootloader .hex and he is long 0xFFF
i tried
Code:
#define LOADER_SIZE                 (0x1FFF)

but the led don't blinks
jeremiah



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PostPosted: Wed Sep 02, 2020 9:15 am     Reply with quote

In the example you posted, you still have #define _bootloader so your application will be in the same address space as your bootloader. Comment that out so that your application is in the correct memory location.

Long term side note: Your define
Code:

#define APPLICATION_END             (getenv("PROGRAM_MEMORY")-1)


is wrong. That will allow you to place code on the same memory PAGE as the FUSES/config bits, essentially erasing them. You'll need to stop on the previous memory PAGE. This is not a problem right now, but if you get a nearly full application, you'll run into problems later.
ciccioc74



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PostPosted: Wed Sep 02, 2020 9:26 am     Reply with quote

thanks for reply

Quote:
In the example you posted, you still have #define _bootloader

yes I know I do a lot of tests. I comment this line to use the bootloader but I leave it to see if the program works[/quote]
Ttelmah



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PostPosted: Wed Sep 02, 2020 9:37 am     Reply with quote

The point is that a USB bootloader is too larger to fit in a 0x1000 space
on a PIC18. The sizes need to be 0x2000, and the bootloader has to
be recompiled with this size, and then reloaded. Then the main code has
to be recompiled with this size, and loaded with the bootloader.
The 0x1000 size is probably for the PIC16 version, which does fit in this
space.
ciccioc74



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PostPosted: Wed Sep 02, 2020 10:02 am     Reply with quote

sorry if I allow myself to insist but at the beginning of the main I read:

Code:
NOTE FOR BUILDING WITH C18 COMPILER:
-------------------------------------------------------------------
This project needs to be built with the full compiler optimizations
enabled, and using the Default storage class "Static" or the total
code size will be too large to fit within the program memory
range 0x000-0xFFF.
Ttelmah



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PostPosted: Wed Sep 02, 2020 10:11 am     Reply with quote

So you are not using the CCS USB bootloader.
You need to actually verify how large the bootloader is building as (look at
.lst file). Problem is that this bootloader may have built in the past to
fit in the 0x1000 space, but with modern compilers may no longer do so.
It's quite common to find code changes in size with different compiler versions
and code that would fit with a V4 compiler no longer will with a V5 compiler....
This will then prevent it from working.

You may well only have to expand the memory a little. It'll need to be a
'page' larger, but I suspect your bootloader is not fitting.
jeremiah



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PostPosted: Wed Sep 02, 2020 10:12 am     Reply with quote

can you post the individual hex files for both the bootloader and the application (compiled to be placed by the bootloader)? Post it using the code tags so it is formatted in a readable matter.
ciccioc74



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PostPosted: Wed Sep 02, 2020 10:38 am     Reply with quote

bootloader
Code:
:020000040000FA
:060000000DEF07F01200F5
:020006000000F8
:0600080004EF08F01200F5
:080018000CEF08F02EEF07F0D9
:020020001200CC
:0E002200010006000000F904000002000000CA
:100030000001E46BE869E969EA69E76B010EEB6FBF
:1000400012000001E4511EE1040108BF93D1000138
:10005000400EFD6F0001600EFB6F000EFC6F2FEC79
:1000600006F00001010EE46FEC6B400EEC5D01E365
:1000700081D1EC51EA6AA00FE96E040EEA22EF6A20
:10008000EC2BF3D700016051080A01E170D1040A9A
:1000900001E131D1050A01E12CD10E0A01E1F5D0CF
:1000A000010A01E1ECD0030A01E194D0010A4CE01D
:1000B000070A40E0010A01E05BD10401020EA06FD3
:1000C0003A0EA16F010EA26FA36FA46B100EA56F65
:1000D000A66BA76BA86B700EA96FAA6BAB6B030E18
:1000E000AC6FAD6BAE6B300EAF6FB06B0E0EB16F11
:1000F000B26BB36BB46B040EB56FB66BB76B200EFF
:10010000B86FB96B080EBA6FBB6BBC6BBD6B020EE0
:10011000BE6FBF6BC06BF00EC16FC26BC36B010EC5
:10012000C46FC56BC66BC769A50ED96F04010CBF40
:1001300021D1DCD00001010EEB6F0001615101E023
:1001400013D10001EB6B10D1400E0001E56FE66B9F
:10015000000EE55D020EE6591FE22FDAE5C000F061
:10016000E6C001F0026A060E1F0BE5C0F6FFE6C00E
:10017000F7FF02C0F8FF06E0D890F636F736F836FB
:10018000E806FAE1940EA66E24DA74EC06F000019B
:10019000E52B000EE623DCD7EC6BECC0A9FFA868CA
:1001A000040EA66E74EC06F014DA0001EC51EC2B90
:1001B000006E016A026AFF0E005C000E0158000E1C
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:00000001FF

blinking RC2


Code:

:0410000018EF08F0ED
:08100800EA6A0B0EE96EEF50DD
:101010000DE00A0E016E006A002EFED7012EFBD7EE
:101020005F0E006E002EFED7EF2EF3D750EF08F0C4
:10103000F86AD09EC150F00BC16E000E0F015B6FBD
:101040005F6F5C6F5D6F5E6F0101886B9A6A996A72
:10105000986A046A056AF29CF29EF2BEFDD7926A13
:10106000896A2B0E926E936A8A6A7C0E936E946ADA
:101070008B6A800E946E956A8C6A000E956E9690BF
:101080009692969496968D6A968096829694968677
:1010900094948B74020E0A6EFA0E0B6E0001B4D794
:1010A0000A2E01D002D00101F7D70101F1D70300C8
:00000001FF
;PIC18F45K50
;CRC=16E6  CREATED="02-set-20 18:35"

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