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Heads up - PIC18F46K80 CCP triggering off wrong edge

 
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newguy



Joined: 24 Jun 2004
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Location: Edmonton, Alberta

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Heads up - PIC18F46K80 CCP triggering off wrong edge
PostPosted: Wed Dec 13, 2017 9:43 am     Reply with quote

A bit of a heads up. Some time back I took a working project and migrated to a slightly different processor - the PIC18F46K80 - as I needed CAN capability. Did the migration, didn't really dig into it much more than "it seems to work" and moved on.

Yesterday I'm preparing some prototype units to be shipped to customers today and...huh...something's not quite right (isn't that always the way - you find stuff just before it's due to be shipped?). Tracked the problem down to CCP5. I set it to trigger from a falling edge but it was also triggering from a rising edge. Here's the kicker - not all units did it. Same FW, same everything, even the processors were from the same lot, but not all would do it. Most would, but not all.

When things calm down a bit I'll open a ticket with Microchip.
Ttelmah



Joined: 11 Mar 2010
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PostPosted: Wed Dec 13, 2017 12:16 pm     Reply with quote

Do a test and see what signal levels the chip is actually responding at.
I noticed an 'oddity' a while ago, that though CCP5 is listed as ST, on some chips it says ST/CMOS, and on some chips it seemed incorrectly to respond well below the ST levels.....
newguy



Joined: 24 Jun 2004
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Location: Edmonton, Alberta

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PostPosted: Wed Dec 13, 2017 5:29 pm     Reply with quote

Given the board/hardware it's not possible to perform such a test. I found the behaviour by sticking a pair of output_high(), output_low() statements in the CCP ISR. I set up the CCP to trigger on a falling edge as I'm expecting a sensor to send data. Data is clocked out of the sensor by toggling that line low - the length of time it's low differentiates a 1 from a 0.

Anyway, the sensor clocks the data sufficiently fast that I cannot feasibly get into the ISR, reconfigure the CCP to trigger on a rising edge, and then exit. The idea here is to measure the width of the low-going pulse. So I cheated a bit (I hate blocking code - I feel dirty doing it) and once I get a low going pulse, I then just wait for x cycles and see if the pulse is low or high (thus getting my 1/0), and exit to wait for the next bit to arrive.

What I found was that I was getting two line toggles - one for the initial falling edge, but on the wide pulses - the one where the line is still low when I exit - I was getting another pair. That can only happen if the CCP was also triggering off a rising edge (and the timing from trigger event to the line toggle indicates that it was the rising edge that was indeed the trigger).
Ttelmah



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PostPosted: Thu Dec 14, 2017 1:36 am     Reply with quote

My thought was that if the thresholds were not actually Schmitt, you might be seeing a low transition on a 'dirty' rising edge.
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