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Warning: PIC18F25K40 undocumented errata
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newguy



Joined: 24 Jun 2004
Posts: 1903

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PostPosted: Thu Sep 07, 2017 7:56 am     Reply with quote
Update: adding the AND gate with clamps to Vdd both upstream and downstream of the gate, along with moving that "return" line to B4 on the PIC has eliminated the weirdness. I also bought a few new processors, just to be sure. I have yet to try the old inventory of PICs with this new layout.

...It's nice to be able to relax again...
Ttelmah



Joined: 11 Mar 2010
Posts: 19260

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PostPosted: Thu Sep 07, 2017 8:21 am     Reply with quote
Well done.
pmuldoon



Joined: 26 Sep 2003
Posts: 218
Location: Northern Indiana

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PostPosted: Wed Sep 13, 2017 7:01 am     Reply with quote
I don't know if making it a ST input instead of TTL would help, but there is a command for this chip to select the input type (default is TTL).
Code:

set_input_level_g(0b11111011);    // 0 = TTL 1 = ST (default)
newguy



Joined: 24 Jun 2004
Posts: 1903

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PostPosted: Wed Sep 13, 2017 7:16 am     Reply with quote
I did try that at the time, but sadly it had no effect.
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