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RF_Developer
Joined: 07 Feb 2011
Posts: 839
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 Posted: Fri Mar 31, 2017 5:16 am |
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| Ttelmah wrote: | I still suspect you are generating a lot of the noise, in how you are testing.
Take a pair of resistors. Say 10K each. Connect them between your supply rails, and put your scope on the junction. Run the code.
How much noise is visible on this pin?. |
This is sound advice. I think, Viki, that you've got hold of the wrong end of the stick on where the noise is coming from. The noise is, as Ttelmah suggests, most likely on the power rails. That does not mean it's generated by or coming from the power supply. Instead, it means that it's generated by your circuitry. Most of it, in all likelihood, comes from the PIC. Where do you think the energy to change SCL comes from? It comes from the power supply via the IO ports on the PIC. The PIC draws current all the time. It is a CMOS device, and while CMOS devices generally draw very little current most of the time, they tend to draw relatively large current spikes when they change state. So a current spike will be drawn every time SCL changes state (and every other signal including the possibly million inside the PIC). That's common basic CMOS knowledge, and yes, there will be no "warning" on the datasheet about it.
This means that we expect some, possibly significant, noise to be on the PIC's power pins, and for much the same reason on on the DAC's power pins. The classic 100nf ceramic (probably) decoupling capacitors are there to reduce the effect, but they cannot eliminate it. Power supplies (or batteries or whatever) do not have zero output impedance - i.e. they cannot deliver infinite current - and will have some transient response to such current spikes, resulting in voltage spikes which you can see with an oscilloscope (if you are careful). These power voltage fluctuations WILL get on to your DAC output, especially, but not only, if the DAC uses the power rail as its reference.
All of the above is basic common knowledge. No datasheet warns about it. It is up to the designer to determine how appropriate a device, layout or configuration is to their application and to take appropriate measures, such as decoupling capacitors and multi-layer PCBs with ground and power planes (which have considerable distributed capacitance and much lower impedance power paths than a conventionally tracked layout) and to select the parts best suited to their specific application.
Personally, as far as I can see, this is mainly a case of over-expectation. The noise, even as it is, is not so bad and the precision appears to be more than sufficient, in what is, as far as I understand it, an small experimenter/hobby application.
If this were a professional application with a tight requirement, such as some precision test equipment, I'd expect you to try several DAC types, spend a fair bit of time carefully designing filters and possibly go through several iteration of PCB layout trying to find the best compromise of complexity/cost/performance. But this really isn't that sort of job, is it? |
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temtronic
Joined: 01 Jul 2010
Posts: 9111
Location: Greensville,Ontario
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| Posted: Fri Mar 31, 2017 6:25 am |
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I'm actually impressed on two fronts.
1) Viki's resolve to 'get to the bottom of it' ! You'd be great in a proper R&D lab where you need to 'find an answer'. You'll be a great tech one day.
2) the ability to puchase a 12 bit DAC on PCB for $3 ! In the late 70s ,when I got into this field (was Avionics tech), a DAC was a huge PCB populated with a LOT of parts costing hundreds, even thousands of dollars.
As previously said , the 'devil's in the details', meaning you need to read every last page of datasheets, application notes, comments from others, etc. Also nothing will work as designed in the Real World...THAT is why bench testing is very important.
Jay |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19224
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| Posted: Fri Mar 31, 2017 7:18 am |
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One other key thing is to repeat the early suggestion to generate a sine wave, not the half wave.
A sine from a DAC, can be heavily filtered above half the sampling frequency. Done carefully this can remove 99% of the digital noise. Then half wave rectify this, and you have a high purity signal the shape required.
Problem is that the half wave signal requires high harmonics to generate the sharp transition at the bottom of each half cycle. This makes filtering hard to do and unnecessarily complex (you need to preserve most of the harmonics 2nd, 3rd, 4th, 5th, 6th, 7th....). Only the first harmonic can be heavily filtered.
One thing that could be done would be to fractionally shift the frequency of the digital bus, so it is not a multiple of the output frequency. This frequency could then be heavily filtered without affecting any of the harmonics. |
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viki2000
Joined: 08 May 2013
Posts: 233
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| Posted: Mon Apr 03, 2017 1:59 am |
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I can do few more tests/measurements as suggested, in order o find how the digital noise of SCL is propagated at the output.
Of course I can try also some other DACs or other methods to generate the rectified sine, even pure analog way, but the discussion turned into another direction and became interesting for me because you say that my circuit is the problem and I say the MCP4725 is a bad boy and I try to prove that. During the next days, when the time will permit, I will answer to your questions above or make some comments at your recommendations.
What I am surprise is that none of you commented a word about MCP4725 (ID APTC) from board Ebay #2.
For me that APTC was as a revelation; was the exception which confirms the rule.
The APTC shows no SCL noise at all at output, no matter on what board is installed.
It tells me that SCL crosstalk noise comes from inside the MCP4725 for most/all the other chips.
What does that tell you? |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19224
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| Posted: Mon Apr 03, 2017 3:20 am |
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No.
You misunderstand slightly. Your circuit _will_ be adding digital noise. So will the DAC. In your early pictures, there were really massive spikes on the level. Note how as you have improved things, these have disappeared. What's left now is a mix of noise from the chip and from your circuit.
You need to understand that if you have circuits with mixed analog and digital circuitry, there _will_ always be crosstalk. You can reduce it, but not ever get rid of it. To design circuits to have really low noise in a digital environment involves a lot of really careful design. Often multiple ground planes, linked back to a single point. Guard tracks. Never routing digital tracks near to analog. Avoiding 90 degree sharp corners on the digital tracks. Reducing input impedances on the analog circuitry. Very careful routing of all power flows in tracks and power/ground planes, etc. etc.
This is what it was hoping to show you with the suggested resistor test. This will show both noise from the supply (there will be some), and some of the induced noise the scope will just pick up. No other circuitry, yet you _will_ see noise.
The crosstalk on the DAC, is specified in the data sheet as less than 10nV/s. This tells you that the noise will depend on just how fast the edge is being fed into the digital input. Feed in something with softer edges (add series resistors to the I2C lines as they feed into the chip), and you will slightly reduce the speed of the signal edges at the chip, and reduce the crosstalk.
Problem is though that your waveform is still going to have the steps from the DAC, and these introduce far more harmonic content than the spikes you now have. Because of the very sharp transition needed at the 0v point on the waveform, you can't filter the signal much without degrading this.
This is why it is so much easier to generate the waveform starting with a sin wave. Your existing circuit generating a sin, could be fed into a low pass filter with a cut off at half the sampling frequency, and you would get a really nice smooth sin. Precision rectify this, and you have your half wave, with minute levels of noise. |
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viki2000
Joined: 08 May 2013
Posts: 233
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| Posted: Mon Apr 03, 2017 5:36 am |
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I never said that will not be noise at all. The problem is its value, how much noise we will see at output.
How much is due to my poor circuit layout PCB and how much comes from inside the MCP4725?
Of course there is noise on VDD or even other pins, but the values that I see and measure are not significant compared with the SCL digital noise seen superimposed at the output of the DAC.
In fact, the small noise values I cannot even measure. If I put the oscilloscope probe to its GND and I go on 10mV scale and high frequency then I see noise without any power supply or circuit, it is the limit of the instrument. I measure pure DC from battery and I see noise, so it is clear the instrument limitation. I do not complain about that.
I can also see noise on VDD, but does not look like SCL crosstalk noise.
I made the measurement that you suggest, but is not too much to see.
All the unused pins of the PIC were soldered together and then connected with 1K resistor to the ground. In code I turned them as output to state logic “0”. I have done that prior the measurements.
When I look in the datasheet of the MCP4725 and I search info about digital noise cross talk I see “Digital Feedthrough” <10nV-s and “Major Code Transition Glitch” as 45nV-s.
What I measure at output as SCL crosstalk noise is 28mV, which is a lot.
There is nowhere else in circuit such high noise crosstalk.
The MCP4725 APTC shows no problems with different boards, indicating that its internal noise/signal reject ratio is better and all the other samples are not good.
I could use a 2nd power supply only for DAC VDD or reference voltage, but I am pretty sure we will see no difference.
The APTC sample demonstrates that is no problem outside of the chip, somewhere on the board.
All the suggestions that you have made above are very good and should be followed when new PCB layout is designed; no doubt about it, but here is a bit more; it is inside the MCP4725. This is what I am trying to point out.
If we look at the block diagram of MCP4725 on the 1st page of the datasheet, we see at output an OpAmp, which you may say that even a small noise not detectable/measurable with my probes/oscilloscopes can be reflected that later in output noise amplified. But then how come MCP4725 APTC shows no problems at output? It is a MCP4725 internal design mistake? It is a faulty chip? I guess not, but rather the other chips.
Generating the rectified sinewave is another subject, but you draw my attention to the noise.
There are 2 more tests that can be done and one of it I will do it in future when I can.
1) I will test on the same PCB, maybe my big PCB, other DACs SOT-23-6 - I just received one from TI and one from Maxim, both 12 bit and SOT-23-6.
2) I could design a small PCB layout, I could upload it here as pdf and when everyone is happy with the design, I can order it, cannot cost so much, and then I can measure again the noise at output, if you want with 2 power supplies or very stable voltage reference IC, having as input battery supply.
My question in the end is: when or what would convince you that SCL noise crosstalk comes from inside the MCP4725 and not from PCB layout or power supply?
https://goo.gl/tAZ5zD |
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temtronic
Joined: 01 Jul 2010
Posts: 9111
Location: Greensville,Ontario
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| Posted: Mon Apr 03, 2017 8:34 am |
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while 'on the test bench'....
It'd be interesting to see what kind of noise is on the outputs of an I2C I/O expander chip.
I did scan the datasheet again and saw a figure that showed both a 10mfd tantlum and a .001 ceramic 'within 4mm'of the power supply pins.
When you consider what's inside the die and how SMALL it is, it's really amazing that anything SMD actually works! Mind you I grew up with vacuum tubes...
Jay |
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viki2000
Joined: 08 May 2013
Posts: 233
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Ttelmah
Joined: 11 Mar 2010
Posts: 19224
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| Posted: Mon Apr 03, 2017 10:49 am |
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You are still ignoring the point. The chip _will_ produce noise, but 'who cares'?.
They tell you what it will generate, and for what it is designed to do, it will be way above the frequencies that matter.
The same is true of every off the shelf DAC, even ones for high quality applications like CD's. However these are normally driven at much higher frequencies (MHz), and with filtering, this doesn't matter at all. This though is why many will specify the output filtration required.
The whole thing started with your trying to produce a 'mains' simulator. As I said right at the start, have you actually looked at mains?. Typically, spikes, misshapen waveforms etc.. If you want a good simulation, you want to be adding noise!...
In fact one way you can reduce this noise, is to actually slow the edges of the I2C. As I said, series resistors on this. Changing the frequency won't work, since it is the edges that matter here. Reducing the pull-ups will slow the rising edge, but won't affect the falling edge. Since 100KHz I2C allows a fall time as slow as 300nSec, slowing this will massively reduce the noise. |
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viki2000
Joined: 08 May 2013
Posts: 233
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| Posted: Mon Apr 03, 2017 11:49 am |
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I am not ignoring the point at all.
I am aware that chip will produce noise, but none of us expected so much. That is the point.
Don’t forget that I started all the above measurements only to prove you that SCL cross-talk noise is not due to my circuit, PCB layout, power supply, oscilloscope, but is coming out of the MCP4725 womb directly. That was the whole point of the last discussions. |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19224
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| Posted: Mon Apr 03, 2017 12:36 pm |
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Your original pictures showed noise many times the levels you now have. This was reduced by redesign. You still have design problems that will be producing significant noise, but you are now down to only about 1.5* the maximum that the data sheet specifies. Note that the data sheet gives the _maximum_. You will get chips that produce less, that is 'luck'.
Always when designing, you need to assume the 'worst case'. |
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viki2000
Joined: 08 May 2013
Posts: 233
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| Posted: Tue Apr 04, 2017 3:10 am |
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My original scope screenshots were done with breadboard and power adapter. The power adapter also introduces certain noise.
When you say “you are now down to only about 1.5* the maximum that the data sheet specifies” at what parameter from datasheet do you refer? What value compared with my measurements?
I would like all the chips to be as the “lucky” one. |
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viki2000
Joined: 08 May 2013
Posts: 233
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| Posted: Tue Apr 04, 2017 3:12 am |
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I have tested MAX5812.
https://datasheets.maximintegrated.com/en/ds/MAX5812.pdf
I have 5 samples. I picked up random one of them marked AAYT, part number MAX5812LEUT.
The code used:
| Code: | #include <16F1825.h>
#fuses NOFCMEN ,NOIESO, NOCLKOUT, BROWNOUT, NOCPD, NOPROTECT, NOMCLR, NOPUT, NOWDT, INTRC_IO
#fuses NOLVP, NODEBUG, BORV19, NOSTVREN, PLL, NOWRT
#use delay(clock=32M)
#use I2C(MASTER, scl=PIN_C4, sda=PIN_C3, FORCE_SW, FAST=400000)
CONST unsigned long SINE_WAVE[38] = {0, 34, 68, 101, 135, 168, 201, 234, 266, 298, 329, 360, 390, 419, 448, 476, 503, 529, 555, 579, 603, 625, 646, 667, 686, 704, 720, 736, 750, 763, 775, 785, 794, 802, 808, 813, 816, 818};
void dac_i2c(unsigned int16 sample){
i2c_start();
i2c_write(0b00100000); // Device address
i2c_write(((sample >> 8) | 0XF0) & 0xCF); // Command + Upper 4 data bits
i2c_write(sample & 0xFF); // Lower bits 8 bits
i2c_stop(); // Stop
}
//MAX5812L with VADD to GND - Address: 0010 000
void main() {
setup_adc(ADC_OFF);
// Turn off al unused pins
output_A(0x00);
output_bit(PIN_C0, 0);
output_bit(PIN_C1, 0);
output_bit(PIN_C2, 0);
output_bit(PIN_C5, 0);
unsigned long int i=0;
disable_interrupts(GLOBAL);
//Power up the MAX5812
i2c_start();
//Below is DAC Address + R/W=0 meaning write
i2c_write(0b00100000);
//This is power up command 01xx00xx
i2c_write(0b01000000);
i2c_stop();
while(TRUE){
while (i< 37){
i++;
//delay_cycles (12);
dac_i2c(SINE_WAVE[i]);
}
while (i>0){
i--;
//delay_cycles (12);
dac_i2c(SINE_WAVE[i]);
}
}
} |
The test:
https://goo.gl/MR78LT
As you can see the noise at output is a lot lower than MCP4725 using the same board, the same components, similar wiring/tracks and the same 400KHz I2C bus. The noise exists, but is low and acceptable and at this level of noise I agree that through a better PCB layout can be even more reduced.
But MCP4725 is a bad boy. |
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RF_Developer
Joined: 07 Feb 2011
Posts: 839
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| Posted: Tue Apr 04, 2017 4:14 am |
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| viki2000 wrote: | I have tested MAX5812.
I have 5 samples. I picked up random one of them marked AAYT, part number MAX5812LEUT.
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All MAX5812LEUTs should be marked AAYT, that is the part marking for the part.
The datasheet quotes the digital feedthrough at 0.2nV-s, compared to 10nV-s for the MCP4725. Guess what? Yes, the feedthrough related noise shouls be much lower, and hey presto it is. That's not magic, that's device specifications.
| Quote: | | But MCP4725 is a bad boy. |
I don't know where this near-obsession with blaming the MCP4725 comes from, but what did you expect? I suspect you had no idea such a thing as digital feedthrough was even possible on DACs.
The choice of parts now seems simple. If you really must have lowest feedthrough noise then yes, the MAX5812 is possibly the chip for you. There may be others (I did say that for a professional application where this was a key parameter I'd expect an engineer to try several DACs to select the most appropriate) but the MAX looks pretty good. But in real engineering design, that's often not the end of it. The price is an important factor, especially in medium to large scale manufacturing. From a well-known UK based distributer, the MAX5812 is £6.10, while the MCP4725 is just £0.84. I know which I'd specify if noise level was not the key factor.
Also there's availability and long-term supply issues: I2C parts are less common and less commonly available than other wise similar SPI parts. That distributer only offers one version of both the MCP and the MAX (not the LEUT btw), so using more than one in an applcation is much more difficult than if I was using SPI.
Then there's a difference inherent in the way I2C works. It's an open-collector bus. Current is drawn all the time when signals are low, but only on the leading edge when they are high (i.e. only to charge the bus capacitance) this intermittant current draw is likely to produce more power rail noise than a solution that draws current more continuously, such as SPI. To get round this you do as Ttelmah says, you increase the I2C pull-ups to give you as slow rise times as is consistent with the bus speed. Less current will be drawn when the signals are low, and less transient current will flow, over a longer time, on each rise. This will reduce noise all round.
Power rail noise is an issue because both these DACs use the power rail as their Vref, as such they are inherently non-precision types becuase power rails will always have more noise than a well-specced and well-designed reference voltage. The problem, from a noise point of view, is that the resistor chain simply pots down the power rail, including all noise. With the DAC at its maximum output (one bit below rail), the noise on the output will be pretty much the same as on the rail.
Noise is a system issue as I tried to explain before. A power supply might produce very little noise when tested on it's own. Switching types commonly, even necessarily, produce much more noise when heavily loaded, but bench testing with a resistive load will not give you the full story. Only by testing with a real, dynamic load, will tell you what happens when the PSU tries to respond to changing load, and anything with a processor will give a load that changes all the time in all sorts of ways, from large medium and long term load changes, say with a motor or heating controller, to sub-nanosecond glitches. Clock noise, at and with the harmonics of the clock rate, is inevitable. No matter how much decoupling you have eand perfect PCB design you do these effects will always be there to some extent: all you can do is reduce them. None of these dynamic effects are going to be there on PSU on its own.
If you use a supply reference DAC, as you are, this noise will, inevitably, make its way to your DAC output in some form or another because that's the way it works.
It's all a system with factors affecting noise levels coming from all over: PSU, layout, references, processors, clock frequencies, data transfer frequecies, rise and fall times, bus capacitance, and yes, even part selection. In engineering as a day job, you generally have to balance all these factors, and factor in other issues such as cost and supply chain and so on.
There are no "bad boys"... |
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viki2000
Joined: 08 May 2013
Posts: 233
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| Posted: Tue Apr 04, 2017 4:42 am |
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| Quote: | | I don't know where this near-obsession with blaming the MCP4725 comes from, but what did you expect? I suspect you had no idea such a thing as digital feedthrough was even possible on DACs. |
I expected nothing.
I did not even think about the feedthrough noise as you said and I do not really care about it in the end, because it goes away a lot through filtering- I have seen that on scope.
My point was only to show that big SCL crosstalk noise of MCP4725 comes mostly from inside the MCP4725 and not so much from my PCB. I agree it is not a very nice PCB layout and there is noise due to the PCB, but not so much as was suggested. I wanted to show that most of the noise is due to the MCP4725 specs or internal design.
This is what I heard most of time that is not a proper PCB. It is not an obsession with MCP4725, I just wanted to prove that any other (better) DAC I2C in similar package SPT-23 with the same PCB will not show the same SCL crosstalk at output. That proves my simple PCB is not the main cause of what we see at MCP4725 output.
The fact that MAX51812 has better specs for digital feedthrough proves again that inside the chip there is less crosstalk and outside of the chip on my lousy PCB there is also less than suggested initially with all MCP4725 tests.
| Quote: | | MAX5812 is £6.10, while the MCP4725 is just £0.84. |
Maybe that is another argument for internal design and the noise at the output of MCP4725. |
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