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rudy
Joined: 27 Apr 2008
Posts: 167
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| 18f2550 fastest internal clock |
 Posted: Mon Apr 25, 2016 4:58 pm |
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Hi there.
How do I configure fuses of 18F2550 to get fastest internal clock with 4MHZ external Crystal.
Regards. |
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asmboy
Joined: 20 Nov 2007
Posts: 2128
Location: albany ny
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| Posted: Mon Apr 25, 2016 5:42 pm |
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may depend on if you are using v 4.x or 5.z
what is your compiler version? |
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temtronic
Joined: 01 Jul 2010
Posts: 9135
Location: Greensville,Ontario
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| Posted: Mon Apr 25, 2016 6:50 pm |
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following the datapaths in the clock diagram.
same for 4550 sister PIC..
4MHz external xtal.....(aka primary osc), nice xtal lots in stock from 16C71 days !
PLL prescalar of 1 -> 4MHz to PLL
give 96MHz to PLL post scalar
so divide by 2 gives
48MHz as the CPU clock speed
I know this works, did it years ago though....
You'll have to consult the 'header' file for the correct names of the 'options'.
Jay |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19264
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| Posted: Tue Apr 26, 2016 12:27 am |
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As a clue/start:
| Code: |
#fuses XTPLL, PLL1, CPUDIV1 //XT using the PLL PLL/2 as the CPU clock
#fuses PUT //required with PLL/crystal
#fuses NOXINST //compiler requires this
#fuses NOLVP, STVREN //For 99% of code should always be set
#use delay(CLOCK=48MHz)
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There are a few more like MCLR, and PBADEN, which may need to be set depending on your hardware (and the watchdog control).
'Beware'. The PLL is often slightly fussy if fed directly with a clock without any divider. You may need perhaps a 200R resistor in series with the crystal to get reliable operation. Depends on the gain of your crystal. |
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rudy
Joined: 27 Apr 2008
Posts: 167
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| Posted: Tue Apr 26, 2016 2:52 am |
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Thank all of you.
Answering asmboy, my compiler is V 5x.
My intention is to use a 4MHZ crystal in primary oscilagor, and work with maximun clock speed as possible, due to extensive I2C call to other components.
Thanks all of you.
Regards. |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19264
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| Posted: Tue Apr 26, 2016 3:45 am |
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I would suggest using 8MHz instead.
On later chips there is no problem with 4MHz. However, these were the first chips to come out with the USB PLL, and I've found that they can be 'fussy' about the 4Mhz oscillator with the PLL, giving odd frequencies sometimes.
I think the PLL requires the oscillator feeding it to have very good clock 'symmetry' (50:50 mark/space), and if a crystal slightly overdrives, the 'raw' 4Mhz can fail to give this. Using 8Mhz, and dividing by 2, gives 50:50 'guaranteed'. |
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rudy
Joined: 27 Apr 2008
Posts: 167
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| Posted: Tue Apr 26, 2016 5:13 am |
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asmboy,
See no problem, I have here 8MHZ, and also 20MHZ.
I think I got the hang of it.
Thanks for all help.
Regards. |
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temtronic
Joined: 01 Jul 2010
Posts: 9135
Location: Greensville,Ontario
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| Posted: Tue Apr 26, 2016 7:05 am |
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What really helps( well, for me...) is to printout the 'clock flow diagram' and then 'highlight' a path from 'source' to CPU .....
This then shows you the various 'blocks' the clock has to go through.
Jay |
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rudy
Joined: 27 Apr 2008
Posts: 167
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| Posted: Tue Apr 26, 2016 7:23 am |
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temtronic, thank you.
I tried that.
Make slight changes here, now the I2c is pretty fast, although I don´t have any idea of how is the speed off the processor and the I2c itself. Now I don´t have time to waste in this matter. Latter, I will go deep on this, and make proper changes if needed.
Regards |
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