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Bootloader clears configuration bits despite WPCFG
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Ttelmah



Joined: 11 Mar 2010
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PostPosted: Wed Sep 03, 2014 8:16 am     Reply with quote
Not sure.
I always have to sit down and draw it out for the different chips. However it says 512 instructions/1536 bytes, and CCS has it as 512/2K (given they 'count' the non existent fourth byte this makes sense).
I must admit the chip variations usually result in me programming a lump larger than a block, then erasing a block, and actually counting how much gets erased to be 'confident'....
jeremiah



Joined: 20 Jul 2010
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PostPosted: Wed Sep 03, 2014 8:26 am     Reply with quote
I took some time to check the data sheet and it seems to fit what I expect. This is the section I pulled from the data sheet on how it is addressed:

Quote:

4.1.1 PROGRAM MEMORY
ORGANIZATION
The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 4-2).
Program memory addresses are always word-aligned
on the lower word and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.


If I read this right, it would go along with my experience of 2 addresses per instruction (16 bit word addressable). If that were the case, a 512 instruction page would be 1024 words or 0x400 in size. That seem correct based on the excerpt?
Ttelmah



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PostPosted: Wed Sep 03, 2014 9:14 am     Reply with quote
Each instruction, is 2*16bit words, so 512instructions would be 1024 words, and 2048 bytes, which is what CCS lists/treats it as. Their memory access functions do everything in bytes not words.
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