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Fuses mismatch

 
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beth.null



Joined: 22 Apr 2010
Posts: 4

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Fuses mismatch
PostPosted: Fri Dec 31, 2010 8:58 am     Reply with quote

Hello to everyone.

I'm writing you about a strange problem I have with the fuses of a file/project.

The target is a 18f67J60 and I am using the icd-u40. The fuses are set on the source code as (I am using the microchip ide/compiler):

#pragma config DEBUG = OFF // Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
#pragma config XINST = ON // Instruction set extension and Indexed Addressing mode enabled
#pragma config STVR = ON // Reset on stack overflow/underflow enabled
#pragma config WDT = OFF // WDT disabled (control is placed on SWDTEN bit)
#pragma config CP0 = OFF // Program memory is not code-protected
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor disabled. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown.
#pragma config IESO = OFF // Two-Speed Start-up disabled
#pragma config FOSC2 = ON // Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
#pragma config FOSC = HS // HS oscillator
#pragma config WDTPS = 2 // Watchdog Timer Postscale Select bits
#pragma config ETHLED = ON // RA0/RA1 are multiplexed with LEDA/LEDB when Ethernet module is enabled and function as I/O when Ethernet is disabled


The problem is that when I generate the .hex file and try to program the chip, first I check the fuses on the ccsload application (File tab, Configuration/ID section) the fuses doesn't match with the specified on the code.

For example I have CP0 dissabled and ccsload says "Code protected from reads", also I have ETHLED = ON and it is dissabled, so I really don't know what is happening.

Maybe ccsload doesn't interpret correctly the fuses on the .hex for this microprocessor?

Have anyone experienced problems like this?

(I don't wan't to code protect the chip accidentally )

Thanks for your support, best regards and happy new year!!!
R2D2



Joined: 10 Jan 2011
Posts: 3

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PostPosted: Mon Jan 10, 2011 4:16 am     Reply with quote

I have the same problem with a PIC18F13k22 using MPLAB ver 8.60
The options in the Fuses menu and the bits in the Config table (file tab in ccsload) do not match the options in MPLAB Configure -> configuration bits. The ccsload version is 4.026. The code is written in MPSAM Assembler 5.37
It would be good to hear a statement from ccs how the configuration bits are set / if it is guaranteed that they are set as set in code.
It is hard enough to establish a programming step in the production line anyway and there is still the option of programming at microchip etc.

For me it is not so important that this problem is solved in terms of using ccsload to configure the configuration bits right but it is very important to make sure the hex file including the configuration bits is downloaded to the chip the exactly the same as with ICD 3 etc. in MPLAB.
R2D2



Joined: 10 Jan 2011
Posts: 3

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PostPosted: Mon Jan 10, 2011 5:53 am     Reply with quote

The config bits of the PIC18F13K22 are from 0x300000 to 0x30000D
(same in PIC18F1xk22.inc, MPLAB and ccsload)
from PIC18F1xk22.inc:
CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED

The hex file of my project at 0x300000:

300000: FF 42 07 00 FF 80 01 FF 00 80 03 C0 03 40 FF FF ; ÿB..ÿ€.ÿ.€.À.@ÿÿ

this matches the code:
; Oscillator Selection bits:
CONFIG FOSC = HS ;HS oscillator
; 4 X PLL Enable bit:
CONFIG PLLEN = OFF ;PLL is under software control
; Primary Clock Enable Bit:
CONFIG PCLKEN = OFF ; Primary clock is under software control
; Fail-Safe Clock Monitor Enable bit:
CONFIG FCMEN = ON ;Fail-Safe Clock Monitor enabled
; Internal/External Oscillator Switchover bit:
CONFIG IESO = OFF ;Oscillator Switchover mode disabled
; Power-up Timer Enable bit:
CONFIG PWRTEN = OFF ;PWRT disabled
; Brown-out Reset Enable bits:
CONFIG BOREN = SBORDIS ;Brown-out Reset enabled in hardware only (SBOREN is disabled)
; Brown Out Voltage:
CONFIG BORV = 30 ; VBOR set to 3.0 V nominal
; Watchdog Timer Enable bit:
CONFIG WDTEN = OFF ;WDT is controlled by SWDTEN bit of the WDTCON register
; Watchdog Timer Postscale Select bits:
CONFIG WDTPS = 1 ;1:1 17 ms 10...30 ms multipliziert mit prescaler
; MCLR Pin Enable bit:
CONFIG MCLRE = ON ;MCLR pin enabled, RA3 input pin disabled
; HFINTOSC Fast Start-up bit:
CONFIG HFOFST = OFF ;The system clock is held off until the HFINTOSC is stable.
; Stack Full/Underflow Reset Enable bit:
CONFIG STVREN = ON ;Stack full/underflow will cause Reset
; Single-Supply ICSP Enable bit:
CONFIG LVP = OFF ;Single-Supply ICSP disabled
; Boot Block Size Select Bit:
CONFIG BBSIZ = OFF ;1kW boot block size
; Extended Instruction Set Enable bit:
CONFIG XINST = OFF ;Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
; Code Protection bit:
CONFIG CP0 = ON ;Block 0 code-protected
; Code Protection bit:
CONFIG CP1 = ON ;Block 1 code-protected
; Boot Block Code Protection bit:
CONFIG CPB = ON ;Boot block code-protected
; Data EEPROM Code Protection bit:
CONFIG CPD = OFF ;Data EEPROM not code-protected ; Lesen möglich
; Bootloader benutzt Tablewrite Befehl auf Block Boot, 0 und 1 aus Block 1
; Write Protection bit:
CONFIG WRT0 = OFF ;Block 0 not write-protected
; Write Protection bit:
CONFIG WRT1 = OFF ;Block 1 not write-protected
; Boot Block Write Protection bit:
CONFIG WRTB = OFF ;Boot block not write-protected
; Configuration Register Write Protection bit:
CONFIG WRTC = ON ;Configuration registers write-protected
; Data EEPROM Write Protection bit:
CONFIG WRTD = OFF ;Data EEPROM not write-protected
; Bootloader benutzt Tableread Befehl auf Block Boot, 0 und 1 aus Block 1 (Verify)
; Table Read Protection bit:
CONFIG EBTR0 = OFF ;Block 0 not protected from table reads executed in other blocks
; Table Read Protection bit:
CONFIG EBTR1 = OFF ;Block 1 not protected from table reads executed in other blocks
; Boot Block Table Read Protection bit:
CONFIG EBTRB = OFF ;Boot block not protected from table reads executed in other blocks

ccsload (PIC18f13k22 selected and tested OK) displays
Config
1 0000
2 0007
3 0000
4 0001
5 8000
6 C003
7 4003

this is not
300000: FF 42 07 00 FF 80 01 FF 00 80 03 C0 03 40 FF FF ; ÿB..ÿ€.ÿ.€.À.@ÿÿ

what configuration bits are programmed?
beth.null



Joined: 22 Apr 2010
Posts: 4

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PostPosted: Tue Jan 11, 2011 1:07 am     Reply with quote

I really don't know what will be programmed, and worst, the tests that I can do are over a EZWeblynx module and I don't want to protect any of this $49 modules.

We need some advice from CCS.

Cheers Beth.
R2D2



Joined: 10 Jan 2011
Posts: 3

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PostPosted: Tue Jan 11, 2011 4:01 am     Reply with quote

I conducted some test and found out that the config bits are porgrammed as set in MPLAB. I did not change anything in ccsload with the config bits, just read out the hexfile.
I programmed with an ICD 2 in MPLAB and compared the readouts with ccsload and MPLAB and the originally generated hexfile.
I saw a mismatch of some Bytes that are not defined in the datasheet and one bit that is given "reads as 1" in the datasheet.
the readouts of ccsload contain an additional information about the controller (in my case ;PIC18F13k22).
The readouts match (not mater if programmed with MPLAB and ICD2 or CCS load and ICD U64) except this line with the controller information.
the mismatch with the compiled hexfile is the same with MPLAB and ccsload.
I did this test with my code protect bits disabled.

@ccs:
maybe a "disable set config bits by ccsload" or "config bits are set in code" checkbox
and a
"disable Test controller set in hexfile <-> hardware" box (for programming a Program for PIC18F13k22 on a PIC18F14k22)
would be good.

Is there anything that could lead to a wrong configuration when generating the hexfile config bits set in code with MPLAB and programming "as compiled" with ccsload?
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