How i2c_isr_state works after an interrupt

[Ttelmah]

The clock is not rising too early.
What you show, is correct behaviour.
The clock line is taken high, so that the data line can be raised with it already high, to signal the 'stop'. The data is read in the high period of the clock. For your whole transfer, the clock high times, are the same, and it reads
1 0 1 0 1 0 1 0 1 0 (MSB to LSB) correctly.
Then the clock line goes high again, for the 'ACK'. The data line is released here, so a '1' is read. At the end of this transaction, the clock is dropped, so that the data line can change (remember lines are only allowed to change in the 'low' periods of the clock time, for normal transactions). As soon as the data line is seen to be low, the clock can go high, then the data line rising, is the 'stop' condition.
The I2C timing diagrams, show dropping at all at this point as 'undefined', with a 'blip' shown on the clock line, with it able to be left high, or drop as the manufacturers see fit.

Best Wishes