Baud Rate Equations in UART

caddy · Joined: 24 Jun 2007 Posts: 14

Hi

I'm trying to calculate the minimum Fosc speed for an application.

The application is MIDI. It transfers at 31250 bps. Each midi 'symbol' consists of 8 bits of data with a start and stop bit making the total 10 bits. If I am correct this means the application needs to run at 31250/10 = 3125 baud. (It is confusing because in the CCS #USE RS232 directive it treats bps and baud as the same thing..)

Currently I am using a PIC18F2620 with 20MHz crystal and the hardware UART. And I want to determine, mathematically, the theoretical minimum speed of crystal I can use. In the 18F2620 datasheet there is a chart on page 206 (example 18-1) that shows how to calculate the baud rate error. However, I've examined these equations and I think the 'error' that they are referring to is actually the accuracy/rounding error of SPBRGH:SPBRG.

Anyway, basically, I would like to know how to calculate the minimum crystal speed I'd need to transfer data at 31250 bps. Any help would be great. I would like to understand how it is worked out, not just get the answer.

Thanks

ckielstra · Joined: 18 Mar 2004 Posts: 3680 Location: The Netherlands

Ttelmah · Guest

On a signalling system, using just two transmission 'states' (on/off), bps, and baud _are_ the same. This is true of the Midi interface, and the PIC async serial interface.
Where the two concepts 'differ', is over something like an audio link, where if (for instance), you sent 16 different 'tones' and could detect all 16, changing tones 1000 times per second, the 'baud' rate would be 1000/sec, but the bps rate, would then potentially be 4* this. (16 states, can transfer 4 bits).
Your baud rate, and your bps rate, are 31250. The _character per second_ rate (cps), is the 3125 figure you derive.
Potentially the slowest clock that could generate this rate, would be this frequency*16. 500000Hz. With the divider set to '0', you get a division by '1', and with BRGH set to one, the prescaler is /16.
At this clock rate, the selectable bps rates, are:
31250(/1), 15625(/2), 10416(/3) etc.. If you wanted a rate of 9600bps (a standard serial rate), the nearest you could get, would be 10416bps (using the /3 divider), or 7812.5bps using /4. The errors for this rate, would then be 8.5% ((10416/9600)-1), or 22.88% for the second possibility.
Slow clocks, bring with them the limitations that you may not be able to do the required work between the characters...

Best Wishes

Ttelmah · Guest

Ckielstra, /4 for the BRG, is only available for sync operation on most PICs. The dividers supported are /16, and /64. The lowest clock is therefore 4* your value. Smile

Again we post simultaneously!...

Best Wishes

ckielstra · Joined: 18 Mar 2004 Posts: 3680 Location: The Netherlands

caddy · Joined: 24 Jun 2007 Posts: 14

Thank you guys, these posts really educated me!

Could someone just explain, how do you set the prescaler to /16 vs /64 within CCS?

Thanks

Ttelmah · Guest

It is set automatically to get the closest rate to the one you request.
Basically, you have a range of possible dividers (on the normal PICs), of 1*16 to 256*16. In steps of '16'. Once the divider needed goes above 4096, the /64 prescaler is selected, and the possible dividers then go from 64*65 to 64*256, in the larger 64 steps. Maximum divider of 16384. If the division is possible using the smaller divider, you get finer control, so this will be automatically selected.
Now, the chip you have (must admit, I missed the chip number...), allows the main divider, to have a range of 1 to 65536, instead of 1 to 256. With this larger range, the prescaler can be smaller, and these chips allow the /4 prescaler to be selected, _only when used with the 16bit divider_, in asynch mode. This gives the value that Ckielstra posted.

Best Wishes