ESD protection/problem for our device/PIC

[Christophe]

Yes a reset matters.. when my PIC resets; the whole device resets with results data loss and a reboot that takes 1 minute.

So the only things I can do is:

* 2 TVS zeners for each pushbutton
* better HF decoupling for all power nets
* 10nF/50V caps parallel on the inputs
* shielding MCLR with ground tracks
* series resistors

[newguy]

Christophe,

Follow the advice you've been given and your circuit will be much more immune to ESD.

You asked what I meant by 'distributed capacitance.' It's standard procedure for me to 'distribute' major electrolytic power supply capacitors throughout my designs. For instance, instead of placing a single 10 uF capacitor near the output of a voltage regulator, my preference is to liberally 'pepper' 3 x 3.3 uF caps around the board or sometimes 5 x 2.2 uF. Cost is a factor, of course, but for my way of thinking it's worth it. I'm probably being way too conservative, but that's the way I am.

My line of thinking is that the caps provide 'local' power. If power is somehow interrupted (ie with ESD), then the large power supply capacitors and their distributed nature ensure that either the effect of the ESD spike is diminished, or that it recovers from it relatively quickly. I place one of these caps relatively close to critical components like a PIC, and the 0.1uF decoupling caps get placed as close to the PIC's supply pins as I can get them.

You may also want to look into placing an MOV (metal oxide varistor) on your power supply line (power - MOV - ground). They're essentially the variable resistor that someone else mentioned, and they're usually standard in any power supply hooked to the mains. They're wonderful at arresting surges/spikes, particularly those caused by electric motors.

[Christophe]

[SherpaDoug]

Generally the caps should go close to the source of the ESD, but more improtantly they should go between the ESD source and the PIC such that there is no way the spike can get to the PIC without the cap diverting it first.

The ground for the caps should lead as directly as possible to the ground point of the ESP current loop, wherever that is. You want to keep the ESD-in, cap, ESD-out loop as short as possible and away from the PIC. Sometimes designers will put an ESD ground ring around the edge of the board which is gorunded at one point. The idea is that ESD currents can run through this ring without disturbing the ground plane used by the rest of the circuitry.
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[Christophe]

So directly connecting it to the PIC ground plane would be wrong?

What do you mean by the ground point of the ESP current loop ?

So I should make a separate ground plane that is only connected through the main plane via 1 small track/connector?

[SherpaDoug]

The ESD is going to come into your product in one place and out at another place. You don't really want it passing through the ground plane under your PIC chip on the way.

If you have a metal box with a keypad and the ESD comes in the keypad and goes out the metal box things are fairly simple. Run lines from the keypad to bypass caps then to the PIC, maybe with a seires impedance like a ferrite bead. The ground side of the caps go to the one mounting hole that electrically connects to the metal box.

If you have a plastic box is gets tougher. But any ESD is still likely to come in some I/O port and out another. If you can run all the IO lines, including power, to one area where they all have bypass caps to a common ground (supernode), then ESD will go in the entrance line, be cap coupled to the supernode, then cap coupled to the exit line, whatever those entrance and exit lines may be. From this I/O bypass area then run lines to the PIC. The PIC ground probably wants to connect to the supernode, but it can do that through a narrow trace, a ferrite bead, or some other restriction.
_________________
The search for better is endless. Instead simply find very good and get the job done.

[Christophe]

Hi,

thanks for the advice; So I've learned that it's important to have separate ESD grounds.

In our product we have an aluminium bottom plate. On that plate is the carrier board mounted via screws on mounting holes. The screws connect with the aluminium plate.

[Christophe]

O yes,

what is the main difference between a TVS zener diode and an ESD cap? It seems to me that they have the same function and that they have the same implementation. Is it best to use them in parallel?

edit:

What about shielding thin ground tracks? Are they a great help?

[SherpaDoug]

The Zener is probably more expensive, but it has less of an effect on the frequency responce of the I/O. If the line carries power or any signal of 9600 baud or slower then caps will do fine. If the signal is faster like 115k baud or video you may have to pay for Zeners. Also Zeners have to be chosen for a specific voltage cutoff.

I am not sure what you mean by shielding thin ground tracks???
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The search for better is endless. Instead simply find very good and get the job done.

[Christophe]

I'm sorry I was unclear:

You want to shield a specific line by routing 2 ground tracks close to it. Someone earlier told me that was useful; but I don't understand why.

[SherpaDoug]

Well that will do a couple of things:
1) It intercepts any leakage current flowing through contamination on the surface of the PCB.
2) It provides a clean return current path so it stops signals on the center track from causing interference with other circuitry.
3) In a simillar way it balances out any magnetic or electrostatic interference that may come from outside sources. Though to be most effective for that you should make sure the two ground traces do not connect to any groundplane in the middle of the run, such as at a via.
4) It also prevents you from routing any other traces too close to the signal. Distance provides isolation of its own.
_________________
The search for better is endless. Instead simply find very good and get the job done.

[MikeValencia]

Make life simple and look at the schematic of the NUF2070MN at onsemi.com

Notice there is an LC filter in between the two TVS diodes. I have a similiar circuit in my application, but it is made up of discrete parts, and does not have the initial TVS.

During the past winter, i've inadvertently zapped the connectors and chassis with my fingers plenty of times each day. It seems to hold up. HOWEVER, on a few occasions, it seems my 50V rated capacitors get "leaky", and my i/o appears noisy. The PIC pin downstream of the tvs stays well protected though. Perhaps the capacitor gets damaged due to lack of the initial TVS.

[Christophe]

So that is a good practice? (shielding ground tracks)
Isn't it better to pour the top layer full of copper connected to the ground plane through via's?

As I've learned here; is it a good practice for ESD compatibility to route the metal housing of the USB connector directly to the mounting hole for the metal bottomplate instead of connecting it directly through the ground plane?

MikeV> I will take a look at that schematic.

[Christophe]

Hi this is how I've implented the advice I got. Can you guys give some feedback.



Per button you have 2 nodes. Per node I have 1 PESD fast zener TVS diode + 1 cap 10nF / 50V. Very close to the pads of the switches. Opposite pads are electrically connected. The copper pour is ground net, connected to pin 13 of the board to board connector. On the other connector that track goes straigt to a chassis mounting hole; it does not connect (earlier) to the pcb's ground plane.