How can I avoid eeprom corruption on power down?

[Guest]

Hi,

I noticed this behavior with the pic... a program thread polls the write-in-progress bit and write to the cell and increment address at each iteration.

Everything goes fine if the power is not removed while the thread is doing its job.

When power fails while a write is being done the cell can assume a value of 255.

I won't be able to change the hardware to put more caps or make it control its own power.

What can I do to avoid this?

Thank you.

[PCM programmer]

1. Change the EEPROM to one that does very fast write operations.
Use a FRAM device from Ramtron for this. http://www.ramtron.com

2. Check the DC input power level (if coming from a wall transformer
or an automobile battery, etc. to your voltage regulator. Let's say
it's nominally 12vdc. Use a voltage divider to scale the nominal
12vdc down to a 0 to 5v range. Apply that input to an A/D pin on
your PIC. Read the voltage immediately before you want to write
to your EEPROM. If it is below 10vdc, then do not start a write
operation.
Check the fall time of the input voltage with an oscilloscope
(preferably a storage scope). Ensure that if the voltage is
at 10vdc, then it will stay above the drop-out voltage of the
voltage regulator for long enough to complete your write operation.

I did both these things on one design and have not had any problems
with corrupted writes.

[PCM programmer]

I think I misinterpreted your post. You're talking about data eeprom
that is internal to the PIC. The comment about using Ramtron doesn't
apply in that case.

[Guest]

The pcb already have the adc to read the power supply, it is sampled at 100hz... Today I attempted to use the last sample to verify if the voltage is still ok but I had some failed writes.

100Hz would give me a 10mS time span, enough I think...
It must be something with the supply fall time, the pcb has 3 47uF for the PIC and one max232.

I must say that it is not normal to cut power while writing to the eeprom... I just don't want any weird things happening.

[Ttelmah]

First question. How many bytes does the thread write?. How often dos the thread write?. Are you aware ofthe life limits of EEPROM?.
Even though this part may have 10 million cycle expected life, if you are writing a value every second for example, this would be used up in just 115 days!. Most of the older chips, only have life expectancies for this memory, of 100K cycles, So, even if you fix the current problem, you could be asking for touble in the future....
The key is power management. If you have a supply rail, which you can tell when the incoming supply has failed (with an AC monitor, or a LVD type circuit), and as soon as this triggers, you switch off all components that draw power, other than the processor itself, it is relatively easy to bring the processor consumption 'down' to something in the order of perhaps 20mA. Instead of continuously writing the data, you write it once the power has failed. Writing four bytes (say) to the EEPROM, takes a total of just 16mSec. If the LVD, triggers at 4.5v say, and the minimum operating voltage for your processor, at the clock rate, is 4.2v (most of the low power chips will go way below this), then you need to have sufficient capacitance on the supply rail, that the supply will fall by no more than 0.3v, at the 20mA current, in 16mSec. This requires:

C=(I.t)/V farads capacitance

C=(0.020*0.016)/0.3 = 0.001067F

So just over 1000uF, could maintain the supply long enough to write four bytes in this circumstance.
Now you would have to allow a little extra (for the time taken to detect the power failure), but for example, I do this on a unit running off a 12v incoming supply. The rail is tested on the input side of the regulator, which is a LDO unit, and can maintain 5v out, down to 6.2v in. If the supply at this point drops below 8v, I trigger the write. The line has to also supply the power for the regulator itself (another mA), but with the greater voltage drop available, 470uF of capacitance, on the input rail, still happily covers the write time.
This code, is interrupt triggered, when the incoming supply drops, and once the write is cplete, simply sits sampling the rail. If it rises again, without the processor stopping, it waits 100mSec, and then restarts the code.
These systems have been used for several years now on some processors, and have never lost a byte.

Best Wishes

[Guest]

[SherpaDoug]

Can you fit two copies of the data? If so you can ping pong between the two and if the latest is corrupt, fall back to the other.
_________________
The search for better is endless. Instead simply find very good and get the job done.

[Ttelmah]

Given that you have got the ability to detect power fail (you talk about having a supply monitor), check this before writing each byte. Given that the write is going to take probably a second (4mSec*256), it is not suprising that there is a problem....

Best Wishes