I2C Master & Slave with 2 PIC's SOLVED

[Ttelmah]

Good.

It's actually potentially 'interesting'. In the PIC, interrupts are only responded
to in the first sub state of the instruction. So anything that results in
an instruction 'not terminating' can prevent interrupt handling.

Now have found references that MicroChip have two different internal
state machines used to handle the I2C master. On one if the slave
holds SCL, the master state machine actually stops inside the transmitting
instruction. When I found this, what had to be happening became 'clear'.

Not good, really a fault with how the I2C hardware is implemented on the
PIC.

[gjs_rsdi]

Hi Ttelmah

You wrote:

[Ttelmah]

The watchdog _will_reset the machine (it is independant of the processor
itself), but the timer counter will not (since the processor is effectively
stopped 'inside' an instruction).
It also won't happen if you can use DMA for this transfer (since then it
is the DMA controller, not the processor kernel itself that is performing
the operation.
However, just use software. For a master, at reasonable clock rates,
software I2C is as fast, and has far fewer issues. One of these things
where the MicroChip hardware is not actually that well designed....

[gjs_rsdi]

Thank you Ttelmah

I remain with the WDT enabled at 16ms in the Master and the Slave.

Best wishes
Joe