| View previous topic :: View next topic |
| Author |
Message |
-Terppa-
Joined: 08 Jan 2018
Posts: 60
Location: Finland
|
| DSPic33ep512mc204 ADC- setup |
 Posted: Fri Feb 24, 2023 2:17 am |
 |
|
Hello PIC programmers!
I have little question about ADC- setup. Is this setup what i use how close the truth.
CPU setup:
| Code: |
#device ADC=10
#device PASS_STRINGS=IN_RAM
#define SYSTEM_CLOCK 70M
#define MYCRYSTAL 16M
#use delay(clock=SYSTEM_CLOCK,crystal=MYCRYSTAL)
|
ADC- setup:
| Code: |
setup_adc_ports(sAN0 | VSS_VDD);
setup_adc(ADC_CLOCK_DIV_32 | ADC_START_ONLY | ADC_TAD_MUL_16);
set_adc_channel(0);
|
1. I was thinking these "ADC_CLOCK_DIV_32" and "ADC_TAD_MUL_16" parameters. My ADC- works but are the "tune" parameters correct in valid clock speed (70Mhz).
2. Is there an easy way to calculate these values because if they are not correct ADC- value can drift.
PCWHD 5.112 + MPLABIDE8.92 + MPLAB plugin
Thank you for your help |
|
 |
Ttelmah
Joined: 11 Mar 2010
Posts: 19966
|
|
| Posted: Fri Feb 24, 2023 3:55 am |
|
|
The answer to this is always, datasheet, datasheet, datasheet.
However in this case you have to go to the special separate sheet for the
ADC module (DS70621).
You seem to be running the ADC very slowly. This chip supports a minimum
Tad of 117.6nSec. Maximum clock 8.5MHz to the ADC. Fp (the clock to
the peripherals) is Fosc/2. so CLOCK_DIV_5 is all you would need. /8 is
the way to go, giving Tad at 228nSec. Then your MUL value is also
massively high.This is the auto sample time. Only needs 4 tad. (worst case).
Depends massively on what frequency you want to measure. With these
values optimised, you can get up to 1M samples/sec. With the values
suggested above, you could get to over 250K samples/sec. With your
current values, just 26K samples/sec. This is actually getting close to
the lowest same rate supported for good accuracy (10k).
However be very aware of just how low the source impedance of the
analog source needs to be for this ADC. Just 200R Max, for optimum
performance. (Parameter AD17 in the data sheet). If you are worried to
get good performance, this needs to be the first thing you look at. |
|
|
-Terppa-
Joined: 08 Jan 2018
Posts: 60
Location: Finland
|
|
| Posted: Fri Feb 24, 2023 4:56 am |
|
|
Thank you very much for the detailed answer
Mr. Ttelmah
I have very lazy sampling rate because i only measure battery voltage. |
|
|
Ttelmah
Joined: 11 Mar 2010
Posts: 19966
|
|
| Posted: Fri Feb 24, 2023 5:29 am |
|
|
Problem is this line in the data sheet:
| Quote: |
If TAD is too long, the voltage on the sampling capacitor can decay
before the conversion is complete.
|
Going slow, is not better. Go too slow and the result can be worse....
I've actually been generous in my figure the figure I gave was for 12bit.
For 10 bit it is half this and you can clock to 13Mhz.
Key to understand is that this chip has a high speed ADC, with a much
smaller sampling capacitor than normal. This brings with it the disadvantage
of needing a very low impedance feed, and supporting only fast rates...
If you are measuring a battery with a resistive divider, you need to add
an external capacitor to the input to give a low AC impedance to charge
the internal capacitor. |
|
|
|
FAQ 
Search
Register
Profile 
Log in to check your private messages 
Log in
