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Sterngleiter
Joined: 07 Jan 2013
Posts: 90
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 Posted: Wed Sep 26, 2018 2:09 pm |
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| what do you mean pic101 sticky? is this a simulation software? |
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Sterngleiter
Joined: 07 Jan 2013
Posts: 90
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| Posted: Wed Sep 26, 2018 2:14 pm |
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| I did not notice that. Of course, both can have the same mode. do I still have to send the 0x01 twice? |
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newguy
Joined: 24 Jun 2004
Posts: 1902
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Ttelmah
Joined: 11 Mar 2010
Posts: 19219
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| Posted: Wed Sep 26, 2018 11:04 pm |
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| You should not have to send 1 twice. It is being missed because of the wrong clock edge... |
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Sterngleiter
Joined: 07 Jan 2013
Posts: 90
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| Posted: Wed Sep 26, 2018 11:31 pm |
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| how should the right clock edge be so that I do not have to send a dummy |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19219
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| Posted: Thu Sep 27, 2018 12:09 am |
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The clock edges is wrong because you have different modes.
Also how is the select line wired on the slave?.
There is another issue, on the first 'dummy' transfer, this will _start_ at the instruction:
spi_xfer(0x01); //single 'send only' transfer to signal start
But, this transfer won't complete for several instruction cycles. So the delay here may be too short.
When you use:
val=spi_xfer(0x01);
This makes the instruction _wait_ for the physical transfer to complete before proceeding.
So, you can either add a dummy read to the first transfer, or wait for the transfer with:
| Code: |
while (!spi_data_is_in())
;
delay_us(50);
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on this first transfer.
Last edited by Ttelmah on Thu Sep 27, 2018 12:17 am; edited 1 time in total |
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Sterngleiter
Joined: 07 Jan 2013
Posts: 90
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| Posted: Thu Sep 27, 2018 12:16 am |
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| As well as Master, CLK=PIN_C3, DI=PIN_C4, DO=PIN_C5 |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19219
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| Posted: Thu Sep 27, 2018 12:48 am |
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That sounds completely wrong....
On you 18F4550, SDI is RB0, SDO is RC7, SCL is RB1, and SS is RA5.
The master SDO needs to go to the slave SDI, and the slave SDO to the master SDI.
You can use any pin you want for a master, but the slave _must_ connect to the actual hardware pins..... |
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Sterngleiter
Joined: 07 Jan 2013
Posts: 90
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| Posted: Thu Sep 27, 2018 12:51 am |
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Why pic18f4550 ? I have pic18f8622
Last edited by Sterngleiter on Thu Sep 27, 2018 12:54 am; edited 1 time in total |
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Sterngleiter
Joined: 07 Jan 2013
Posts: 90
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| Posted: Thu Sep 27, 2018 12:52 am |
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| Pic18f8622 |
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Sterngleiter
Joined: 07 Jan 2013
Posts: 90
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| Posted: Thu Sep 27, 2018 12:53 am |
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| I Know, MISO, MOSI , CLK , CS is right |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19219
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| Posted: Thu Sep 27, 2018 1:12 am |
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You have never told us the processor number for your slave....
The 8622, uses RD7 for SS.
It also has some quite nasty errata on SPI. :( |
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Sterngleiter
Joined: 07 Jan 2013
Posts: 90
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| Posted: Thu Sep 27, 2018 1:16 am |
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| I use SPI_1 , SS is the Pin_f7. Pin_D7 is for SPI_2 |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19219
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| Posted: Thu Sep 27, 2018 1:23 am |
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Good.
The point is it's a classic case of omitting stuff. You posted code carefully 'leaving out' the processor part and not telling us how stuff is actually wired. Don't be surprised if we then query things when you do this....
A little table like:
MASTER SLAVE
SDO C7 SDI C4
SDI C4 SDO C7
CS C2 SS F7
SCK C3 SCK C3
Chip is PIC18F8622 clocked at?.... |
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Sterngleiter
Joined: 07 Jan 2013
Posts: 90
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| Posted: Thu Sep 27, 2018 1:38 am |
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you're right. I should have written.
Pin_C5 is by SPI_1 Data out(SDO) Not c7.
I think the wiring is correct.
Master. SLave
pin_c3 (clk) —— pin_c3 clk
Pin_c4 (SDI) —— pin_c5 ( SDO )
Pin_c5 (SDO) —— pin_c4 ( SDI )
Pin_c2 ( CS) —— pin_f7 ( SS )
8mhz internal |
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