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Hardware SPI best practice
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blowtorch



Joined: 11 Jun 2013
Posts: 35
Location: Cape Town

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PostPosted: Thu Jun 28, 2018 12:58 pm     Reply with quote

Hi Ttelmah

There are 2 SPI busses in the MRF89 - one is for reading / writing registers, max speed 6MHz, in the manual they refer to the CS line for this as CSCON. Then there is the FIFO, for reading & writing data that is received or to be transmitted. This has its own chip select known as CSDAT, this SPI connection has a 1MHz restriction.

As you say, the FIFO is a 1 byte _write_, multiple byte _read_. operation. The register access, on the other hand, as you saw is supposed to allow multiple register writes. Hence the apparent contradiction in the data sheet.

After my experience, I do not use continuous, but rather play it safe and sacrifice a tiny bit of efficiency and do separate transactions per register. That debacle over setting up all the registers probably cost me a whole day of dev time.

It's a complex chip (accordingly to my limited experience and knowledge). 32 registers with a total of 79 settable options, 2 interrupt lines, 2 SPI connections. Many of the registers are straightforward to set up, but some gave me trouble, like my initial attempts of understanding FTXRXIREG & FTPRIREG, which configure the 2 interrupt lines.

I eventually mapped out all the registers in an excel spreadsheet, this was useful as a learning aid as well as easily being able to check my code that does the bit masking which is required to be able to change only certain bits in a register. I am thinking at some stage I may create structs for all the registers just to make the code easier to understand.

One can download the Microchip MiWi protocol demo code which includes a driver & header file for the MRX89XA, this was very useful in understanding how to set it up. Their code is a bit of a nightmare to wade through though, with gazillions of ifndef, goto's etc. My usage scenario is more simple, with a many to one relationship with multiple TX, and only 1 RX.

This is my first foray into rf, and it was most gratifying to see a rude message pop up on the rx LCD display signifying the first successful tx / rx transaction Very Happy
Ttelmah



Joined: 11 Mar 2010
Posts: 19195

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PostPosted: Thu Jun 28, 2018 1:25 pm     Reply with quote

Agreed. However if you look at the chip functional diagrams both busses are being handled by the same 'control interface'. Creates an interesting suggestion that they are going to behave the same in many areas.
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