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[SOLVED] CLKOUT waveform?
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PCM programmer



Joined: 06 Sep 2003
Posts: 20385

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PostPosted: Sat May 12, 2018 1:47 am     Reply with quote

newguy wrote:

64MHz: misshapen positive offset 0.5Vp-p waveform out.
48MHz: misshapen positive offset 1.5Vp-p waveform out.
32MHz: proper rail-rail output square wave.
16MHz: proper rail-rail output square wave.
12MHz: proper rail-rail output square wave.
8MHz: proper rail-rail output square wave.
4MHz: misshapen positive offset 2Vp-p waveform out.
2MHz: misshapen positive offset 1Vp-p waveform out.
1MHz: misshapen positive offset 0.5Vp-p waveform out.

I ran all your freqs on my 18F47K40 and got the results shown below:

64MHz: misshapen positive offset 0.5Vp-p waveform out.
48MHz: misshapen positive offset 1.0Vp-p waveform out.
32MHz: not a perfect square wave, 0.2v to 3.3v waveform out
16MHz: proper rail-rail output square wave.
12MHz: proper rail-rail output square wave.
8MHz: proper rail-rail output square wave.
4MHz: proper rail-rail output square wave.
2MHz: proper rail-rail output square wave.
1MHz: proper rail-rail output square wave.

This makes more 'sense' as it starts failing at 32 MHz a little bit
and gets worse the higher you go.

PIC Silicon rev: a003
Date code: 1729YAK
Package: PDIP-40
Supplier: Digikey
Vdd voltage: 3.3v
Programmer: Pickit 3
Programmer software: Microchip IPE vs. 4.15
Compiler IDE: Microchip vs. 8.92
CCS Compiler vs.: 5.078

Also, I tested it at 5v for the 48 and 64 MHz freqs. Same results.

You could add this data to your trouble ticket.
Ttelmah



Joined: 11 Mar 2010
Posts: 13536

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PostPosted: Sat May 12, 2018 2:43 am     Reply with quote

Suggestion.

Clear the SLRCON registers. SLRCONA, SLRCONB & SLRCONC. Do something like:
Code:

#byte SLRCONA=getenv("SFR:SLRCONA")
#byte SLRCONB=getenv("SFR:SLRCONB")
#byte SLRCONC=getenv("SFR:SLRCONC")

//Then in your main
    SLRCONA=SLRCONB=SLRCONC=0;



These all default to '1' which implies slew rate limiting is enabled. Though the limitation should still allow the clock rates involved, it's worth trying with this off....
PCM programmer



Joined: 06 Sep 2003
Posts: 20385

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PostPosted: Sat May 12, 2018 2:55 am     Reply with quote

Yes Ttelmah, that fixed it for all the higher frequencies. Thanks.
newguy



Joined: 24 Jun 2004
Posts: 1517
Location: Edmonton, Alberta

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PostPosted: Sat May 12, 2018 8:09 am     Reply with quote

Ttelmah wrote:
Suggestion.

Clear the SLRCON registers. SLRCONA, SLRCONB & SLRCONC. Do something like:
Code:

#byte SLRCONA=getenv("SFR:SLRCONA")
#byte SLRCONB=getenv("SFR:SLRCONB")
#byte SLRCONC=getenv("SFR:SLRCONC")

//Then in your main
    SLRCONA=SLRCONB=SLRCONC=0;



These all default to '1' which implies slew rate limiting is enabled. Though the limitation should still allow the clock rates involved, it's worth trying with this off....


I'll try that Monday. Thanks!
Ttelmah



Joined: 11 Mar 2010
Posts: 13536

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PostPosted: Sat May 12, 2018 8:52 am     Reply with quote

Very Happy

It's interesting since it seems to suggest that the actual slew rate limits are 'worse' than the data sheet suggests. However at least we have a 'reason' now.
The slew rate limit is meant to limit the rise and fall times to 25nSec each, which should allow a cycle at 50nSec, so 20MHz. It suggests it's actually giving perhaps half this....
It does say "These parameters are characterized but not tested" for the maximum slew time.

I looked at this, when the clock reference module gave the same behaviour, since this implied the problem was with the output pin drive itself, and not the signal feeding it.
newguy



Joined: 24 Jun 2004
Posts: 1517
Location: Edmonton, Alberta

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PostPosted: Mon May 14, 2018 12:41 pm     Reply with quote

Confirmed, the slew rate control was preventing both the CLKOUT and CLKR signals from reaching their full output excursion and thus was limiting the apparent bandwidth. Thanks Ttelmah.
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