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TI CC1101
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guy



Joined: 21 Oct 2005
Posts: 284

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PostPosted: Sat Apr 25, 2020 12:26 pm     Reply with quote

See my previous answer from May 29, 2017 10:48 am.
PCM programmer



Joined: 06 Sep 2003
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PostPosted: Sun Apr 26, 2020 1:44 pm     Reply with quote

guy is referring to his answer to lscantillo's question in this post:
http://www.ccsinfo.com/forum/viewtopic.php?t=54957&start=18
vmetal2020



Joined: 25 Apr 2020
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PostPosted: Wed Apr 29, 2020 11:44 am     Reply with quote

Yes I know. I have checked the continuity between PIC and CC1101 and it is ok. Do you think that the problem is a bad connection of GDO0?
guy



Joined: 21 Oct 2005
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PostPosted: Wed Apr 29, 2020 2:24 pm     Reply with quote

vmetal2020 wrote:
Yes I know. I have checked the continuity between PIC and CC1101 and it is ok. Do you think that the problem is a bad connection of GDO0?

The documentation I made in the code is wrong - there is a mixup between GDO0 and GDO2.
Code:
 // Wait for GDO0 to be set -> sync transmitted
   while(!input(GDO2)) {

Check GDO2 with an oscilloscope and see if it goes high. If it does then check your code to setup GDO2 correctly (set to input, digital, etc.)
Sorry I can't check your code for you...
vmetal2020



Joined: 25 Apr 2020
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PostPosted: Thu Apr 30, 2020 8:36 am     Reply with quote

I got it!, I hadn't written the configuration of output pins.

Thank you.

I attached my code for help other person.
Code:

#include <pruebaccs_sensorpuerta.h>

#define   LED      PIN_A3

// manual/software SPI
#define MOSI   PIN_C5
#define   MISO   PIN_C4
#define   SCK      PIN_C3
#define   GDO2   PIN_B0// unused
#define   CS      PIN_A5
#define   GDO0   PIN_B1

#DEFINE   BUF_SIZE   100
byte txBuffer[BUF_SIZE];
byte rxBuffer[BUF_SIZE];
byte rxPacketLen=0;

#define WRITE_BURST     0x40
#define READ_SINGLE     0x80
#define READ_BURST      0xC0

// Defines
#define CRC_OK              0x80
#define RSSI                0
#define LQI                 1
#define BYTES_IN_RXFIFO     0x7F       

// CCxxxx STROBE, CONTROL AND STATUS REGSITERS
#define CCxxx0_IOCFG2 0x00 // GDO2 output pin configuration
#define CCxxx0_IOCFG1 0x01 // GDO1 output pin configuration
#define CCxxx0_IOCFG0 0x02 // GDO0 output pin configuration
#define CCxxx0_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
#define CCxxx0_SYNC1 0x04 // Sync word, high int8
#define CCxxx0_SYNC0 0x05 // Sync word, low int8
#define CCxxx0_PKTLEN 0x06 // Packet length
#define CCxxx0_PKTCTRL1 0x07 // Packet automation control
#define CCxxx0_PKTCTRL0 0x08 // Packet automation control
#define CCxxx0_ADDR 0x09 // Device address
#define CCxxx0_CHANNR 0x0A // Channel number
#define CCxxx0_FSCTRL1 0x0B // Frequency synthesizer control
#define CCxxx0_FSCTRL0 0x0C // Frequency synthesizer control
#define CCxxx0_FREQ2 0x0D // Frequency control word, high int8
#define CCxxx0_FREQ1 0x0E // Frequency control word, middle int8
#define CCxxx0_FREQ0 0x0F // Frequency control word, low int8
#define CCxxx0_MDMCFG4 0x10 // Modem configuration
#define CCxxx0_MDMCFG3 0x11 // Modem configuration
#define CCxxx0_MDMCFG2 0x12 // Modem configuration
#define CCxxx0_MDMCFG1 0x13 // Modem configuration
#define CCxxx0_MDMCFG0 0x14 // Modem configuration
#define CCxxx0_DEVIATN 0x15 // Modem deviation setting
#define CCxxx0_MCSM2 0x16 // Main Radio Control State Machine configuration
#define CCxxx0_MCSM1 0x17 // Main Radio Control State Machine configuration
#define CCxxx0_MCSM0 0x18 // Main Radio Control State Machine configuration
#define CCxxx0_FOCCFG 0x19 // Frequency Offset Compensation configuration
#define CCxxx0_BSCFG 0x1A // Bit Synchronization configuration
#define CCxxx0_AGCCTRL2 0x1B // AGC control
#define CCxxx0_AGCCTRL1 0x1C // AGC control
#define CCxxx0_AGCCTRL0 0x1D // AGC control
#define CCxxx0_WOREVT1 0x1E // High int8 Event 0 timeout
#define CCxxx0_WOREVT0 0x1F // Low int8 Event 0 timeout
#define CCxxx0_WORCTRL 0x20 // Wake On Radio control
#define CCxxx0_FREND1 0x21 // Front end RX configuration
#define CCxxx0_FREND0 0x22 // Front end TX configuration
#define CCxxx0_FSCAL3 0x23 // Frequency synthesizer calibration
#define CCxxx0_FSCAL2 0x24 // Frequency synthesizer calibration
#define CCxxx0_FSCAL1 0x25 // Frequency synthesizer calibration
#define CCxxx0_FSCAL0 0x26 // Frequency synthesizer calibration
#define CCxxx0_RCCTRL1 0x27 // RC oscillator configuration
#define CCxxx0_RCCTRL0 0x28 // RC oscillator configuration
#define CCxxx0_FSTEST 0x29 // Frequency synthesizer calibration control
#define CCxxx0_PTEST 0x2A // Production test
#define CCxxx0_AGCTEST 0x2B // AGC test
#define CCxxx0_TEST2 0x2C // Various test settings
#define CCxxx0_TEST1 0x2D // Various test settings
#define CCxxx0_TEST0 0x2E // Various test settings

// Strobe commands
#define CCxxx0_SRES 0x30 // Reset chip.
#define CCxxx0_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL = 1).
// If in RX / TX: Go to a wait state where only the synthesizer is
// Running (for quick RX / TX turnaround).
#define CCxxx0_SXOFF 0x32 // Turn off crystal oscillator.
#define CCxxx0_SCAL 0x33 // Calibrate frequency synthesizer and turn it off
// (Enables quick start).
#define CCxxx0_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and
// MCSM0.FS_AUTOCAL = 1.
#define CCxxx0_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if
// MCSM0.FS_AUTOCAL = 1. If in RX state and CCA is enabled:
// Only go to TX if channel is clear.
#define CCxxx0_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit
// Wake-On-Radio mode if applicable.
#define CCxxx0_SAFC 0x37 // Perform AFC adjustment of the frequency synthesizer
#define CCxxx0_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio)
#define CCxxx0_SPWD 0x39 // Enter power down mode when CSn goes high.
#define CCxxx0_SFRX 0x3A // Flush the RX FIFO buffer.
#define CCxxx0_SFTX 0x3B // Flush the TX FIFO buffer.
#define CCxxx0_SWORRST 0x3C // Reset real time clock.
#define CCxxx0_SNOP 0x3D // No operation. May be used to pad strobe commands to two
// int8s for simpler software.
#define CCxxx0_PARTNUM 0x30
#define CCxxx0_VERSION 0x31
#define CCxxx0_FREQEST 0x32
#define CCxxx0_LQI 0x33
#define CCxxx0_RSSI 0x34
#define CCxxx0_MARCSTATE 0x35
#define CCxxx0_WORTIME1 0x36
#define CCxxx0_WORTIME0 0x37
#define CCxxx0_PKTSTATUS 0x38
#define CCxxx0_VCO_VC_DAC 0x39
#define CCxxx0_TXBYTES 0x3A
#define CCxxx0_RXBYTES 0x3B
#define CCxxx0_PATABLE 0x3E
#define CCxxx0_TXFIFO 0x3F
#define CCxxx0_RXFIFO 0x3F

/////////////////////////////////////

//Configure the CC1101 module by reading or writing to configuration
//register through SPI interface. SPI serial interface consists of four lines:
//MOSI: Master Output Slave Input (master write)
//MISO: Master Input Slave Output (master read)
//SCK: Serial clock signal, controlled by master
//CSN: chip select signal, low active
// <SPI write and read Code>
int8 SpiTxRxByte (int8 dat) {
   int8 i, temp;

   temp = 0;
   output_low(SCK);   //SCK = 0;
   for (i = 0; i <8; i ++) {
      if (dat & 0x80) output_high(MOSI);
      else output_low(MOSI);
     
      dat <<= 1;
      delay_us(1);
      output_high(SCK);
      temp <<= 1;
      if (input(MISO)) temp ++;
      delay_us(1);
      output_low(SCK);
   }
   return temp;
}

/////////////////////////////

// Configure the CC1101 module through the SPI interface, reading and writing
//into configuration register>
int8 halSpiReadReg (int8 addr) {
   int8 temp, value;
   temp = addr | READ_SINGLE; // read register command
   output_low(CS);
   while (input(MISO));
   SpiTxRxByte (temp);
   value = SpiTxRxByte (0);
   output_high(CS);
   return value;
}

/////////////////////////////

//void halSpiWriteReg (int8 addr, int8 value)
void halRfWriteReg (int8 addr, int8 value) {
   output_low(CS);
   while (input(MISO));
   SpiTxRxByte (addr); // write address
   SpiTxRxByte (value); // write configuration
   output_high(CS);
}

/////////////////////////////

void halSpiWriteBurstReg(BYTE addr, BYTE count) {
    INT8 i;

   output_low(CS);
   while (input(MISO));
    SpiTxRxByte(addr | WRITE_BURST);
    delay_us(10);
    for (i = 0; i < count; i++) {
      SpiTxRxByte(txBuffer[i]);
        //SPI_WAIT();
        delay_us(10);   //???
    }
   output_high(CS);
}

////////////////////////////////

void halSpiStrobe(BYTE strobe) {
   output_low(CS);
   while (input(MISO));
   SpiTxRxByte (strobe); // write address
   output_high(CS);
}

////////////////////////////////

BYTE halSpiReadStatus(BYTE addr) {
    INT8 x;

   output_low(CS);
   while (input(MISO));
   SpiTxRxByte (addr|READ_BURST);
   // SPI_WAIT
   x=SpiTxRxByte (0);
   // SPI_WAIT
   output_high(CS);
    return x;
}

/////////////////////////////////////

   
void halSpiReadBurstReg(BYTE addr, BYTE count) {
    INT8 i;
    byte x;

   output_low(CS);
   while (input(MISO));
   SpiTxRxByte (addr|READ_BURST);
//    SPI_WAIT();
   if(count>(BUF_SIZE-5)) count=BUF_SIZE-5;
    for (i = 0; i < count; i++) {
       x=SpiTxRxByte (0);
        //SPI_WAIT();
        rxBuffer[i] = x;
    }
   output_high(CS);
}

/////////////////////////////////////

// Configure CC1101
void halRfWriteRfSettings (void) {
//
// Rf settings for CC1101
//
// export from SmartRF studio
// 433.92MHz 1.2Kbaud, 10dB
// GFSK, dev. 5KHz, RX filter BW 58KHz
   halRfWriteReg(CCxxx0_IOCFG0,0x06);  //GDO0 Output Pin Configuration
   halRfWriteReg(CCxxx0_FIFOTHR,0x47); //RX FIFO and TX FIFO Thresholds
   halRfWriteReg(CCxxx0_SYNC1,0x7A);   //Sync Word, High Byte
   halRfWriteReg(CCxxx0_SYNC0,0x0E);   //Sync Word, Low Byte
   halRfWriteReg(CCxxx0_PKTLEN,0x14);  //Packet Length
   halRfWriteReg(CCxxx0_PKTCTRL0,0x05);//Packet Automation Control
   halRfWriteReg(CCxxx0_FSCTRL1,0x06); //Frequency Synthesizer Control
   halRfWriteReg(CCxxx0_FREQ2,0x10);   //Frequency Control Word, High Byte
   halRfWriteReg(CCxxx0_FREQ1,0xB0);   //Frequency Control Word, Middle Byte
   halRfWriteReg(CCxxx0_FREQ0,0x73);   //Frequency Control Word, Low Byte
   halRfWriteReg(CCxxx0_MDMCFG4,0xF5); //Modem Configuration
   halRfWriteReg(CCxxx0_MDMCFG3,0x83); //Modem Configuration
   halRfWriteReg(CCxxx0_MDMCFG2,0x12); //Modem Configuration
   halRfWriteReg(CCxxx0_MDMCFG1,0x21); //Modem Configuration
   halRfWriteReg(CCxxx0_DEVIATN,0x15); //Modem Deviation Setting
   halRfWriteReg(CCxxx0_MCSM0,0x18);   //Main Radio Control State Machine Configuration
   halRfWriteReg(CCxxx0_FOCCFG,0x16);  //Frequency Offset Compensation Configuration
   halRfWriteReg(CCxxx0_AGCCTRL2,0x43);//AGC Control
   halRfWriteReg(CCxxx0_AGCCTRL1,0x49);//AGC Control
   halRfWriteReg(CCxxx0_WORCTRL,0xFB); //Wake On Radio Control
   halRfWriteReg(CCxxx0_FSCAL3,0xE9);  //Frequency Synthesizer Calibration
   halRfWriteReg(CCxxx0_FSCAL2,0x2A);  //Frequency Synthesizer Calibration
   halRfWriteReg(CCxxx0_FSCAL1,0x00);  //Frequency Synthesizer Calibration
   halRfWriteReg(CCxxx0_FSCAL0,0x1F);  //Frequency Synthesizer Calibration
   halRfWriteReg(CCxxx0_TEST2,0x81);   //Various Test Settings
   halRfWriteReg(CCxxx0_TEST1,0x35);   //Various Test Settings
   halRfWriteReg(CCxxx0_TEST0,0x09);   //Various Test Settings
   
   halRfWriteReg(CCxxx0_PATABLE,0xC0);   // 10dB
   //halRfWriteReg(CCxxx0_PATABLE,0x60);   // 0dB
}

/////////////////////////////////////////

void halRfSendPacket (int8 size) {
// put data in txBuffer
   halRfWriteReg (CCxxx0_TXFIFO, size);
      halSpiWriteBurstReg (CCxxx0_TXFIFO, size); // write the data to be sent
   halSpiStrobe (CCxxx0_STX); // send data into the transmit mode
   
   // Wait for GDO0 to be set -> sync transmitted
   while(!input(GDO0)) {
      //halSpiStrobe(CCxxx0_SNOP); //possible
   }
   // Wait for GDO0 to be cleared -> end of packet
   while(input(GDO0)) {
//      halSpiStrobe(CCxxx0_SNOP); interrupts
   }
   halSpiStrobe (CCxxx0_SFTX);
 
}

//////////////////////////////////////////
int8 halRfReceivePacket () {
// before calling set rxPacketLen!
// data will be stored in rxBuffer and rxPacketLen changed accordingly
   INT8 status [2];
   INT8 packetLength;
   byte tmp0,tmp1;

   halSpiStrobe (CCxxx0_SRX); // entry into the receiving state
   
   while (! input(GDO0));
   while (input(GDO0));
   if ((halSpiReadStatus (CCxxx0_RXBYTES) & BYTES_IN_RXFIFO)) // If the pick is not 0 bytes
   {
      packetLength = halSpiReadReg (CCxxx0_RXFIFO);
      if (packetLength <= rxPacketLen) {
         halSpiReadBurstReg (CCxxx0_RXFIFO, packetLength);
         rxPacketLen = packetLength; // receive data to modify the length of the current data
         // Read the 2 appended status bytes (status [0] = RSSI, status [1] = LQI)
         tmp0=rxBuffer[0];
         tmp1=rxBuffer[1];
         halSpiReadBurstReg (CCxxx0_RXFIFO, 2); // read CRC, bit
         halSpiStrobe (CCxxx0_SFRX); // receive buffer wash
         status[0]=rxBuffer[0];
         status[1]=rxBuffer[1];
         // restore rxBuffer data:
         rxBuffer[0]=tmp0;
         rxBuffer[1]=tmp1;
         return (status[1] & CRC_OK); // return successfully received if the verification is successful
      }
      else
      {
         rxPacketLen = packetLength;
         halSpiStrobe (CCxxx0_SFRX); // receive buffer wash
         return 0;
      }
   }
   else
   return 0;
}

/////////////////////////////////////
/////////////////////////////////////
/////////////////////////////////////

void main() {
   //printf("INICIO\r\n");
   //delay_ms(1000);
   byte i,bp;

   // issue manual POR sequence and SRES:
   //restart_wdt();
   output_high(LED);
   output_high(PIN_A2);
   delay_ms(400);
   output_high(CS);
   output_high(SCK);
   output_low(MOSI);
   // strobe CS low/high
   delay_us(10);
   output_low(CS);
   delay_us(10);
   output_high(CS);
   output_low(SCK);   // MY
   delay_us(40);
   output_low(CS);
   delay_us(10);
   // wait for CHIP_RDYn :
   while (input(MISO));
   // SRES:
   delay_us(10);
   halSpiStrobe(CCxxx0_SRES);
   
   delay_ms(1);
   halRfWriteRfSettings();
//   i=halSpiReadReg(CCxxx0_FREQ0); for write-read test

   delay_ms(1);
// TX:   
   for(i=0;i<10;i++) {
      txBuffer[i]=i+0x40;
   }
   //printf("2\r\n");
   while(1) {
      delay_ms(1000);
      //printf("3\r\n");
      halRfSendPacket(10);
      //printf("Despues del sendpacket\r\n");
      output_low(LED);
      delay_ms(1000);
      output_high(LED);
      delay_ms(1000);
      //printf("Envio\r\n");
      //restart_wdt();
   }
}



.h
Code:
#include <18F25K20.h>
#device ADC=10
#FUSES NOWDT                    //No Watch Dog Timer
#use delay(internal=16MHz)
#use FIXED_IO( A_outputs=PIN_A5,PIN_A3,PIN_A2 )
#use FIXED_IO( C_outputs=PIN_C5,PIN_C3 )
//#use rs232(baud=115200,parity=N,xmit=PIN_C6,rcv=PIN_C7,bits=8,stream=PORT1)
#define Ledrojo   PIN_A2
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