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18f452 clock problem

 
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micro



Joined: 10 Sep 2003
Posts: 13

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18f452 clock problem
PostPosted: Fri Feb 20, 2004 8:14 am     Reply with quote

I am using PIC18F452 with 40MHz externat XTAL osc. I wrote a code that has spi port configurations and application. But when I listen to SCLK pin, I see approx 3MHz clock frequency..This is the first time using this series. Before, I used 16f8xx series. My code snipped is below. Could give me any advise about the problem.. Thanks..

#include <16f877.h>
#device *=16
#fuses HS,NOWDT,NOPROTECT,NOLVP
#use delay(clock=20000000)
#use standard_io(B)
#use rs232 (baud=9600, xmit=PIN_C6, rcv=PIN_C7,ERRORS)
#use standard_io(A)
#use standard_io(D)

void main(void)
{

int32 count;
int16 time=0xFFF8;
int pn=0;

output_high(LED1);
setup_adc(ADC_OFF);
setup_adc_ports(NO_ANALOGS);
setup_psp(PSP_ENABLED);
enable_interrupts(GLOBAL);
enable_interrupts(INT_PSP);

setup_spi(spi_master |spi_l_to_h |spi_clk_div_4);

bit_clear(*0x14,4); // ------> CKP
bit_clear(*0x94,6);// ------> CKE

while(1)
{
spi_write(0x55);
delay_us(20);
}

}
Neutone



Joined: 08 Sep 2003
Posts: 839
Location: Houston

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PostPosted: Fri Feb 20, 2004 8:19 am     Reply with quote

I would have guessed closer to 2.5Mhz.

40Mhz crystle = 10 Mhz instruction clock.

Your dividing it by 4

setup_spi(spi_master |spi_l_to_h |spi_clk_div_4);

Try a diferent divider.
micro



Joined: 10 Sep 2003
Posts: 13

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PostPosted: Fri Feb 20, 2004 8:36 am     Reply with quote

I use the code snipped below but it gives error (undefined identifier!)..I think the problem is diffrent.

setup_spi(spi_master |spi_l_to_h |spi_clk_div_1);


Clock division could be minimum spi_clk_div_4. I use same code for 16f877 and 20 MHz external XTAL osc, I see 5 MHz clock on SCLK pin. What the problem is about the 18f452.

With 40 MHz external osc , it must be 10 MHz instruction cycle? İt that is true, when I use setup_spi(spi_master |spi_l_to_h |spi_clk_div_4),
it must be 10 Mhz SPI clock. Musn't it?
Neutone



Joined: 08 Sep 2003
Posts: 839
Location: Houston

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PostPosted: Fri Feb 20, 2004 9:10 am     Reply with quote

Try a divider of 64 or 16

With the exception of when PLL is used the instruction cycles are 1/4 the speed of the crystle. PLL makes it 1 for 1 but is only usable on crystles 10Mhz and lower. It is also only an option on the PIC18 series.
dvsoft



Joined: 28 Nov 2003
Posts: 46

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PostPosted: Fri Feb 20, 2004 9:12 am     Reply with quote

hello

you use 40Mhz external XTAL?? or 10Mhz Xtal with PLL
micro



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PostPosted: Fri Feb 20, 2004 9:29 am     Reply with quote

I am using 40 MHZ external XTAL without PLL. May it a problem? What is the max value for external XTAL using without PLL. ?
Neutone



Joined: 08 Sep 2003
Posts: 839
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PostPosted: Fri Feb 20, 2004 9:56 am     Reply with quote

Try
setup_spi(SPI_MASTER |SPI_H_TO_L | SPI_CLK_DIV_64 );

It's what I use.
mvaraujo



Joined: 20 Feb 2004
Posts: 59
Location: Brazil

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PostPosted: Fri Feb 20, 2004 12:03 pm     Reply with quote

In order to keep lower EMI, i would rather use a 10MHz Xtal and clock multiplied by 4 in hardware. I have a config running like that fine.

My configs and fuses are:

Code:

#use delay(clock=40000000)       // clock de 40MHz
#fuses H4,NOOSCSEN,NOWDT,PUT,NOPROTECT,NOBROWNOUT,NOSTVREN,NOLVP,NODEBUG      // config bits
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